From d2ecaaca3404a05ba65bb6756bc5fbd05389ed2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Wed, 29 Mar 2023 10:57:17 +0200 Subject: [PATCH 01/16] netifd: update to version 2023-05-31 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Contains following changes: * bridge: bridge_dump_info: add dumping of bridge attributes * bridge: make it more clear why the config was applied * cmake: fix build by reordering the cflags definitions * treewide: fix multiple compiler warnings Signed-off-by: Petr Štetiar --- package/network/config/netifd/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/network/config/netifd/Makefile b/package/network/config/netifd/Makefile index 8dcff7987d..8d179beb30 100644 --- a/package/network/config/netifd/Makefile +++ b/package/network/config/netifd/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/netifd.git -PKG_SOURCE_DATE:=2023-04-17 -PKG_SOURCE_VERSION:=7de5440a520f9c6687358c7ef88ac4aad0ff98a5 -PKG_MIRROR_HASH:=aaf6aef1c991c67b6ef43b4c7f102ba94319bf522f620e93293d031b8333bd8f +PKG_SOURCE_DATE:=2023-05-31 +PKG_SOURCE_VERSION:=38cbdc1c8cbbe2e30d62227d74565bd3fa21a36b +PKG_MIRROR_HASH:=c275ef1f550726b045b3dd7bcee1d660bba9d56c4d53bf32f1eeb6f68bc4116c PKG_MAINTAINER:=Felix Fietkau PKG_LICENSE:=GPL-2.0 From 8d4a2bb8f9f3709e9a9351072a4ddd7b1003ca86 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 24 May 2023 00:03:12 +0200 Subject: [PATCH 02/16] kernel: disable new v6.1 DRM option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not many platforms use the DRM configs but Gemini use it so make sure to disable all new kernel v6.1 features that we do not want to get prompted about. Signed-off-by: Linus Walleij Signed-off-by: Petr Štetiar [rebased] --- target/linux/generic/config-6.1 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/generic/config-6.1 b/target/linux/generic/config-6.1 index 6b422f084d..0c31acfd12 100644 --- a/target/linux/generic/config-6.1 +++ b/target/linux/generic/config-6.1 @@ -1603,6 +1603,7 @@ CONFIG_DQL=y # CONFIG_DRM_I2C_NXP_TDA998X is not set # CONFIG_DRM_I2C_SIL164 is not set # CONFIG_DRM_I915 is not set +# CONFIG_DRM_ITE_IT6505 is not set # CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ITE_IT6505 is not set # CONFIG_DRM_ITE_IT66121 is not set From 567784127e92ba6f9291adb1a546f567e50d9850 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Fri, 26 May 2023 11:38:24 +0200 Subject: [PATCH 03/16] ci: bump buildworker container to version v6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Its being used by buildbot workers, adds g++-multilib to fix node cross-compilation from a 64-bit build machine to 32-bit host. References: https://github.com/openwrt/buildbot/pull/7 Signed-off-by: Petr Štetiar --- .github/workflows/Dockerfile.tools | 2 +- .github/workflows/build-tools.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/Dockerfile.tools b/.github/workflows/Dockerfile.tools index df5892618a..5d365fc56d 100644 --- a/.github/workflows/Dockerfile.tools +++ b/.github/workflows/Dockerfile.tools @@ -1,4 +1,4 @@ -FROM ghcr.io/openwrt/buildbot/buildworker-v3.8.0:v2 +FROM ghcr.io/openwrt/buildbot/buildworker-v3.8.0:v6 COPY --chown=buildbot staging_dir/host /prebuilt_tools/staging_dir/host COPY --chown=buildbot build_dir/host /prebuilt_tools/build_dir/host diff --git a/.github/workflows/build-tools.yml b/.github/workflows/build-tools.yml index 9b865f2608..0629b1b62a 100644 --- a/.github/workflows/build-tools.yml +++ b/.github/workflows/build-tools.yml @@ -13,7 +13,7 @@ jobs: build: name: Build tools runs-on: ubuntu-latest - container: ghcr.io/openwrt/buildbot/buildworker-v3.8.0:v2 + container: ghcr.io/openwrt/buildbot/buildworker-v3.8.0:v6 steps: - name: Checkout From 95dde523297c652072ee96ac32d22912a43ef761 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Fri, 26 May 2023 11:41:18 +0200 Subject: [PATCH 04/16] ci: build: verify downloaded toolchain tarball MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CDNs are known to ship outdated or corrupted files, if it unpacks correctly, it necessarily doesn't mean, that we're using the desired content. So lets fix it by checking the tarball as well. I'm adding GPG checking explicitly, its not needed, but just double checking, that everything is working as expected on build infrastructure. Signed-off-by: Petr Štetiar --- .github/workflows/build.yml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index efaf759403..367a43383b 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -280,13 +280,23 @@ jobs: restore-keys: | ccache-${{ inputs.ccache_type }}-${{ inputs.target }}/${{ inputs.subtarget }}- + - name: Import GPG keys + shell: su buildbot -c "sh -e {0}" + if: inputs.build_toolchain == false && steps.parse-toolchain.outputs.toolchain-type != 'internal' && steps.parse-toolchain.outputs.toolchain-type != 'external_container' + run: gpg --receive-keys 0xCD84BCED626471F1 0x1D53D1877742E911 0xCD54E82DADB3684D + - name: Download external toolchain/sdk if: inputs.build_toolchain == false && steps.parse-toolchain.outputs.toolchain-type != 'internal' && steps.parse-toolchain.outputs.toolchain-type != 'external_container' shell: su buildbot -c "sh -e {0}" working-directory: openwrt run: | - wget -O - https://downloads.cdn.openwrt.org/${{ env.TOOLCHAIN_PATH }}/targets/${{ inputs.target }}/${{ inputs.subtarget }}/${{ env.TOOLCHAIN_FILE }}.tar.xz \ - | tar --xz -xf - + wget https://downloads.cdn.openwrt.org/${{ env.TOOLCHAIN_PATH }}/targets/${{ inputs.target }}/${{ inputs.subtarget }}/${{ env.TOOLCHAIN_FILE }}.tar.xz + wget https://downloads.cdn.openwrt.org/${{ env.TOOLCHAIN_PATH }}/targets/${{ inputs.target }}/${{ inputs.subtarget }}/sha256sums.asc + wget https://downloads.cdn.openwrt.org/${{ env.TOOLCHAIN_PATH }}/targets/${{ inputs.target }}/${{ inputs.subtarget }}/sha256sums + gpg --with-fingerprint --verify sha256sums.asc + sha256sum --check --ignore-missing sha256sums + tar --xz -xf ${{ env.TOOLCHAIN_FILE }}.tar.xz + rm ${{ env.TOOLCHAIN_FILE }}.tar.xz sha256sums - name: Configure testing kernel if: inputs.testing == true From f597f34f3afa7bba8a2606490617688f1cea5a44 Mon Sep 17 00:00:00 2001 From: Jeffery To Date: Wed, 31 May 2023 21:58:34 +0800 Subject: [PATCH 05/16] build: export GIT_CEILING_DIRECTORIES for package builds A package may run git as part of its build process, and if the package source code is not from a git checkout, then git may traverse up the directory tree to find buildroot's repository directory (.git). For instance, Poetry Core, a Python build backend, will read the contents of .gitignore for paths to exclude when creating a Python package. If it finds buildroot's .gitignore file, then Poetry Core will exclude all of the package's files[1]. This exports GIT_CEILING_DIRECTORIES for both package and host builds so that git will not traverse beyond $(BUILD_DIR)/$(BUILD_DIR_HOST). [1]: https://github.com/python-poetry/poetry/issues/5547 Signed-off-by: Jeffery To --- include/host-build.mk | 1 + include/package.mk | 1 + 2 files changed, 2 insertions(+) diff --git a/include/host-build.mk b/include/host-build.mk index b7fb0a737f..7485f91e42 100644 --- a/include/host-build.mk +++ b/include/host-build.mk @@ -131,6 +131,7 @@ define Host/Exports/Default $(1) : export STAGING_PREFIX=$$(HOST_BUILD_PREFIX) $(1) : export PKG_CONFIG_PATH=$$(STAGING_DIR_HOST)/lib/pkgconfig:$$(HOST_BUILD_PREFIX)/lib/pkgconfig $(1) : export PKG_CONFIG_LIBDIR=$$(HOST_BUILD_PREFIX)/lib/pkgconfig + $(1) : export GIT_CEILING_DIRECTORIES=$$(BUILD_DIR_HOST) $(if $(HOST_CONFIG_SITE),$(1) : export CONFIG_SITE:=$(HOST_CONFIG_SITE)) $(if $(IS_PACKAGE_BUILD),$(1) : export PATH=$$(TARGET_PATH_PKG)) endef diff --git a/include/package.mk b/include/package.mk index f03cb15f05..c391d320aa 100644 --- a/include/package.mk +++ b/include/package.mk @@ -194,6 +194,7 @@ define Build/Exports/Default $(1) : export CONFIG_SITE:=$$(CONFIG_SITE) $(1) : export PKG_CONFIG_PATH:=$$(PKG_CONFIG_PATH) $(1) : export PKG_CONFIG_LIBDIR:=$$(PKG_CONFIG_PATH) + $(1) : export GIT_CEILING_DIRECTORIES:=$$(BUILD_DIR) endef Build/Exports=$(Build/Exports/Default) From 595608eb3f05cba31da59e0d5d82504ab6731c0b Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Wed, 31 May 2023 15:19:31 +0200 Subject: [PATCH 06/16] kernel: fix wrong detection of Linux-Testing-Version in makefile DUMP When the split was done, the case for testing kernel version wasn't handled and only the to-be-compiled kernel version details files was included. This cause the kernel Linux-Testing-Version output from makefile target DUMP to report only the kernel version without the minor version (example 6.1 instead of 6.1.29). This value is expected with the full kernel version and this cause the dump-target-info.pl script to not correctly identify if a target have a testing kernel for the kernels calls. Fix this regression by correctly including the kernel details files if the target declare support for a testing kernel version. Fixes: 0765466a42f4 ("kernel: split kernel version to dedicated files") Signed-off-by: Christian Marangi --- include/kernel-version.mk | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/kernel-version.mk b/include/kernel-version.mk index 1edb01df27..958ed9be0c 100644 --- a/include/kernel-version.mk +++ b/include/kernel-version.mk @@ -13,6 +13,15 @@ endif include $(KERNEL_DETAILS_FILE) +ifdef KERNEL_TESTING_PATCHVER + KERNEL_TESTING_DETAILS_FILE=$(INCLUDE_DIR)/kernel-$(KERNEL_TESTING_PATCHVER) + ifeq ($(wildcard $(KERNEL_TESTING_DETAILS_FILE)),) + $(error Missing kernel version/hash file for $(KERNEL_TESTING_PATCHVER). Please create $(KERNEL_TESTING_DETAILS_FILE)) + endif + + include $(KERNEL_TESTING_DETAILS_FILE) +endif + remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1)))) sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1))))))) From fd572feef80c2366af7ce68775708b21948e1018 Mon Sep 17 00:00:00 2001 From: Tony Ambardar Date: Tue, 30 May 2023 22:14:13 -0700 Subject: [PATCH 07/16] kernel: 6.1: add missing CONFIG_TEST_DYNAMIC_DEBUG option This new option (default N) will generate prompts building with OpenWrt configs that set CONFIG_KERNEL_DYNAMIC_DEBUG=y. Fix this by adding the disabled option to the generic config. Signed-off-by: Tony Ambardar --- target/linux/generic/config-6.1 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/generic/config-6.1 b/target/linux/generic/config-6.1 index 0c31acfd12..74a2a3e3a7 100644 --- a/target/linux/generic/config-6.1 +++ b/target/linux/generic/config-6.1 @@ -6681,6 +6681,7 @@ CONFIG_TCP_CONG_CUBIC=y # CONFIG_TEST_CLOCKSOURCE_WATCHDOG is not set # CONFIG_TEST_DEBUG_VIRTUAL is not set # CONFIG_TEST_DIV64 is not set +# CONFIG_TEST_DYNAMIC_DEBUG is not set # CONFIG_TEST_FIRMWARE is not set # CONFIG_TEST_FREE_PAGES is not set # CONFIG_TEST_HASH is not set From 3c55d8698a4a8236939a551d44adb6dbfea7c085 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Tue, 30 May 2023 22:00:19 +0200 Subject: [PATCH 08/16] kernel: Make kmod-phylink depend on kmod-libphy The CONFIG_PHYLINK Kconfig option in the kernel selects CONFIG_LIBPHY. Add this dependency to fix the all kernel modules build on MIPS malta and armvirt with kernel 6.1. With kernel 5.15 mod-phylink and kmod-sfp are empty packages because no OpenWrt kmod is selecting a module which needs sfp or phylink support. Fixes: #12758 Signed-off-by: Hauke Mehrtens --- package/kernel/linux/modules/netdevices.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk index 934ba3c4f2..948902cf63 100644 --- a/package/kernel/linux/modules/netdevices.mk +++ b/package/kernel/linux/modules/netdevices.mk @@ -111,6 +111,7 @@ $(eval $(call KernelPackage,libphy)) define KernelPackage/phylink SUBMENU:=$(NETWORK_DEVICES_MENU) TITLE:=Model for MAC to optional PHY connection + DEPENDS:=+kmod-libphy KCONFIG:=CONFIG_PHYLINK FILES:=$(LINUX_DIR)/drivers/net/phy/phylink.ko AUTOLOAD:=$(call AutoLoad,15,phylink,1) From 0f6b8e65161a840c57d86dfb8fb61d018798c0a1 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Tue, 30 May 2023 22:04:20 +0200 Subject: [PATCH 09/16] kernel: Make kmod-usb-net-smsc95xx depend on kmod-net-selftests The smsc95xx driver got selftest support with kernel 5.18, add the new dependency fixing the all kernel modules build on MIPS malta with kernel 6.1. Signed-off-by: Hauke Mehrtens --- package/kernel/linux/modules/usb.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/kernel/linux/modules/usb.mk b/package/kernel/linux/modules/usb.mk index f9b00fabd8..721e17f970 100644 --- a/package/kernel/linux/modules/usb.mk +++ b/package/kernel/linux/modules/usb.mk @@ -1285,7 +1285,7 @@ $(eval $(call KernelPackage,usb-net-smsc75xx)) define KernelPackage/usb-net-smsc95xx TITLE:=SMSC LAN95XX based USB 2.0 10/100 ethernet devices - DEPENDS:=+kmod-libphy +kmod-phy-smsc + DEPENDS:=+kmod-libphy +kmod-phy-smsc +LINUX_6_1:kmod-net-selftests KCONFIG:=CONFIG_USB_NET_SMSC95XX FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/smsc95xx.ko AUTOLOAD:=$(call AutoProbe,smsc95xx) From 2d5f3b3c4ce4c6221299f2362b3029783048f649 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 20 May 2023 13:56:00 +0200 Subject: [PATCH 10/16] airoha: spi-en7523: Fix compile warning The set_spi_clock_speed() function is not used, this causes a compile warning which results in a build error with -WError. Signed-off-by: Hauke Mehrtens --- ...spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/linux/airoha/patches-5.15/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch b/target/linux/airoha/patches-5.15/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch index 8df11630c7..6c21666ed1 100644 --- a/target/linux/airoha/patches-5.15/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch +++ b/target/linux/airoha/patches-5.15/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch @@ -25,7 +25,7 @@ obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o --- /dev/null +++ b/drivers/spi/spi-en7523.c -@@ -0,0 +1,311 @@ +@@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include @@ -166,6 +166,7 @@ + } +} + ++#if 0 +static void set_spi_clock_speed(int freq_mhz) +{ + u32 tmp, val; @@ -178,6 +179,7 @@ + tmp |= (val << 8) | 1; + writel(tmp, ENSPI_CLOCK_DIVIDER); +} ++#endif + +static void init_hw(void) +{ From 043f8a4f5ecf00e8a62b5a5d48baba48e620ea6a Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Tue, 30 May 2023 12:59:07 +0800 Subject: [PATCH 11/16] uboot-rockchip: add Orange Pi R1 Plus support Add support for the Xunlong Orange Pi R1 Plus. Manually generated of-platdata files to avoid swig dependency. Signed-off-by: Tianling Shen --- package/boot/uboot-rockchip/Makefile | 8 + ...28-Add-support-for-Orange-Pi-R1-Plus.patch | 564 ++++++++++++++++++ .../orangepi-r1-plus-rk3328/dt-decl.h | 24 + .../orangepi-r1-plus-rk3328/dt-plat.c | 170 ++++++ .../orangepi-r1-plus-rk3328/dt-structs-gen.h | 55 ++ 5 files changed, 821 insertions(+) create mode 100644 package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch create mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h create mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c create mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index bdd1f5d5d8..126af6ac54 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -45,6 +45,13 @@ define U-Boot/nanopi-r2s-rk3328 friendlyarm_nanopi-r2s endef +define U-Boot/orangepi-r1-plus-rk3328 + $(U-Boot/rk3328/Default) + NAME:=Orange Pi R1 Plus + BUILD_DEVICES:= \ + xunlong_orangepi-r1-plus +endef + define U-Boot/roc-cc-rk3328 $(U-Boot/rk3328/Default) NAME:=ROC-RK3328-CC @@ -87,6 +94,7 @@ UBOOT_TARGETS := \ rockpro64-rk3399 \ nanopi-r2c-rk3328 \ nanopi-r2s-rk3328 \ + orangepi-r1-plus-rk3328 \ roc-cc-rk3328 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes diff --git a/package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch b/package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch new file mode 100644 index 0000000000..ff17559c2f --- /dev/null +++ b/package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch @@ -0,0 +1,564 @@ +From ff312af37d5f263f181468639aab83f645d331f1 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 20 May 2023 18:50:38 +0800 +Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus + +Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong. + +This device is similar to the NanoPi R2S, and has a 16MB +SPI NOR (mx25l12805d). The reset button is changed to +directly reset the power supply, another detail is that +both network ports have independent MAC addresses. + +The device tree and description are taken from kernel v6.3-rc1. + +Reviewed-by: Kever Yang +Signed-off-by: Tianling Shen +--- + arch/arm/dts/Makefile | 1 + + .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 46 +++ + arch/arm/dts/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++ + board/rockchip/evb_rk3328/MAINTAINERS | 6 + + configs/orangepi-r1-plus-rk3328_defconfig | 114 ++++++ + 5 files changed, 540 insertions(+) + create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus.dts + create mode 100644 configs/orangepi-r1-plus-rk3328_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ + rk3328-evb.dtb \ + rk3328-nanopi-r2c.dtb \ + rk3328-nanopi-r2s.dtb \ ++ rk3328-orangepi-r1-plus.dtb \ + rk3328-roc-cc.dtb \ + rk3328-rock64.dtb \ + rk3328-rock-pi-e.dtb +--- /dev/null ++++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +@@ -0,0 +1,46 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd ++ * (C) Copyright 2020 David Bauer ++ */ ++ ++#include "rk3328-u-boot.dtsi" ++#include "rk3328-sdram-ddr4-666.dtsi" ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; ++ }; ++}; ++ ++&gpio0 { ++ u-boot,dm-spl; ++}; ++ ++&pinctrl { ++ u-boot,dm-spl; ++}; ++ ++&sdmmc0m1_gpio { ++ u-boot,dm-spl; ++}; ++ ++&pcfg_pull_up_4ma { ++ u-boot,dm-spl; ++}; ++ ++/* Need this and all the pinctrl/gpio stuff above to set pinmux */ ++&vcc_sd { ++ u-boot,dm-spl; ++}; ++ ++&gmac2io { ++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++}; ++ ++&spi0 { ++ spi_flash: spiflash@0 { ++ u-boot,dm-pre-reloc; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts +@@ -0,0 +1,359 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Based on rk3328-nanopi-r2s.dts, which is: ++ * Copyright (c) 2020 David Bauer ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include "rk3328.dtsi" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus"; ++ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; ++ ++ aliases { ++ mmc0 = &sdmmc; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac_clk: gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; ++ pinctrl-names = "default"; ++ ++ led-0 { ++ function = LED_FUNCTION_LAN; ++ color = ; ++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-1 { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led-2 { ++ function = LED_FUNCTION_WAN; ++ color = ; ++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&sdmmc0m1_gpio>; ++ pinctrl-names = "default"; ++ regulator-name = "vcc_sd"; ++ regulator-boot-on; ++ vin-supply = <&vcc_io>; ++ }; ++ ++ vcc_sys: vcc-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vdd_5v_lan: vdd-5v-lan-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&lan_vdd_pin>; ++ pinctrl-names = "default"; ++ regulator-name = "vdd_5v_lan"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&display_subsystem { ++ status = "disabled"; ++}; ++ ++&gmac2io { ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; ++ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; ++ clock_in_out = "input"; ++ phy-handle = <&rtl8211e>; ++ phy-mode = "rgmii"; ++ phy-supply = <&vcc_io>; ++ pinctrl-0 = <&rgmiim1_pins>; ++ pinctrl-names = "default"; ++ snps,aal; ++ rx_delay = <0x18>; ++ tx_delay = <0x24>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rtl8211e: ethernet-phy@1 { ++ reg = <1>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ rk805: pmic@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-0 = <&pmic_int_l>; ++ pinctrl-names = "default"; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_io>; ++ vcc6-supply = <&vcc_sys>; ++ ++ regulators { ++ vdd_log: DCDC_REG1 { ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io: DCDC_REG4 { ++ regulator-name = "vcc_io"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_18: LDO_REG1 { ++ regulator-name = "vcc_18"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc18_emmc: LDO_REG2 { ++ regulator-name = "vcc18_emmc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_10: LDO_REG3 { ++ regulator-name = "vdd_10"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&io_domains { ++ pmuio-supply = <&vcc_io>; ++ vccio1-supply = <&vcc_io>; ++ vccio2-supply = <&vcc18_emmc>; ++ vccio3-supply = <&vcc_io>; ++ vccio4-supply = <&vcc_io>; ++ vccio5-supply = <&vcc_io>; ++ vccio6-supply = <&vcc_io>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gmac2io { ++ eth_phy_reset_pin: eth-phy-reset-pin { ++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ lan { ++ lan_vdd_pin: lan-vdd-pin { ++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; ++ pinctrl-names = "default"; ++ vmmc-supply = <&vcc_sd>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <50000000>; ++ }; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <0>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&u2phy { ++ status = "okay"; ++}; ++ ++&u2phy_host { ++ status = "okay"; ++}; ++ ++&u2phy_otg { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb20_otg { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; +--- a/board/rockchip/evb_rk3328/MAINTAINERS ++++ b/board/rockchip/evb_rk3328/MAINTAINERS +@@ -18,6 +18,12 @@ F: configs/nanopi-r2s-rk3328_defcon + F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi + F: arch/arm/dts/rk3328-nanopi-r2s.dts + ++ORANGEPI-R1-PLUS-RK3328 ++M: Tianling Shen ++S: Maintained ++F: configs/orangepi-r1-plus-rk3328_defconfig ++F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi ++ + ROC-RK3328-CC + M: Loic Devulder + M: Chen-Yu Tsai +--- /dev/null ++++ b/configs/orangepi-r1-plus-rk3328_defconfig +@@ -0,0 +1,98 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO_SUPPORT=y ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_ROCKCHIP_RK3328=y ++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_TPL_LIBCOMMON_SUPPORT=y ++CONFIG_TPL_LIBGENERIC_SUPPORT=y ++CONFIG_SPL_DRIVERS_MISC_SUPPORT=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEBUG_UART_BASE=0xFF130000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYSINFO=y ++CONFIG_DEBUG_UART=y ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 ++# CONFIG_ANDROID_BOOT_IMAGE is not set ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb" ++CONFIG_MISC_INIT_R=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_TPL_SYS_MALLOC_SIMPLE=y ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_I2C_SUPPORT=y ++CONFIG_SPL_POWER_SUPPORT=y ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_TPL_OF_CONTROL=y ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_TPL_OF_PLATDATA=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_TPL_DM=y ++CONFIG_REGMAP=y ++CONFIG_SPL_REGMAP=y ++CONFIG_TPL_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_SYSCON=y ++CONFIG_TPL_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_FASTBOOT_BUF_ADDR=0x800800 ++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=20000000 ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_SPL_RAM=y ++CONFIG_TPL_RAM=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++# CONFIG_TPL_SYSRESET is not set ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_TPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h new file mode 100644 index 0000000000..75795aa6cc --- /dev/null +++ b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h @@ -0,0 +1,24 @@ +/* + * DO NOT MODIFY + * + * Declares externs for all device/uclass instances. + * This was generated by dtoc from a .dtb (device tree binary) file. + */ + +#include +#include + +/* driver declarations - these allow DM_DRIVER_GET() to be used */ +extern U_BOOT_DRIVER(rockchip_rk3328_cru); +extern U_BOOT_DRIVER(rockchip_rk3328_dmc); +extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); +extern U_BOOT_DRIVER(ns16550_serial); +extern U_BOOT_DRIVER(rockchip_rk3328_spi); +extern U_BOOT_DRIVER(rockchip_rk3328_grf); + +/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ +extern UCLASS_DRIVER(clk); +extern UCLASS_DRIVER(mmc); +extern UCLASS_DRIVER(ram); +extern UCLASS_DRIVER(serial); +extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c new file mode 100644 index 0000000000..90656fc306 --- /dev/null +++ b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c @@ -0,0 +1,170 @@ +/* + * DO NOT MODIFY + * + * Declares the U_BOOT_DRIVER() records and platform data. + * This was generated by dtoc from a .dtb (device tree binary) file. + */ + +/* Allow use of U_BOOT_DRVINFO() in this file */ +#define DT_PLAT_C + +#include +#include +#include + +/* + * driver_info declarations, ordered by 'struct driver_info' linker_list idx: + * + * idx driver_info driver + * --- -------------------- -------------------- + * 0: clock_controller_at_ff440000 rockchip_rk3328_cru + * 1: dmc rockchip_rk3328_dmc + * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc + * 3: serial_at_ff130000 ns16550_serial + * 4: spi_at_ff190000 rockchip_rk3328_spi + * 5: syscon_at_ff100000 rockchip_rk3328_grf + * --- -------------------- -------------------- + */ + +/* + * Node /clock-controller@ff440000 index 0 + * driver rockchip_rk3328_cru parent None + */ +static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { + .reg = {0xff440000, 0x1000}, + .rockchip_grf = 0x38, +}; +U_BOOT_DRVINFO(clock_controller_at_ff440000) = { + .name = "rockchip_rk3328_cru", + .plat = &dtv_clock_controller_at_ff440000, + .plat_size = sizeof(dtv_clock_controller_at_ff440000), + .parent_idx = -1, +}; + +/* + * Node /dmc index 1 + * driver rockchip_rk3328_dmc parent None + */ +static struct dtd_rockchip_rk3328_dmc dtv_dmc = { + .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, + 0xff720000, 0x1000, 0xff798000, 0x1000}, + .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, + 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15, + 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0, + 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8, + 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8, + 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104, + 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114, + 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184, + 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, + 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c, + 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, + 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, + 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, + 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, + 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, + 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, + 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x79, 0x9}, +}; +U_BOOT_DRVINFO(dmc) = { + .name = "rockchip_rk3328_dmc", + .plat = &dtv_dmc, + .plat_size = sizeof(dtv_dmc), + .parent_idx = -1, +}; + +/* + * Node /mmc@ff500000 index 2 + * driver rockchip_rk3288_dw_mshc parent None + */ +static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { + .bus_width = 0x4, + .cap_sd_highspeed = true, + .clocks = { + {0, {317}}, + {0, {33}}, + {0, {74}}, + {0, {78}},}, + .disable_wp = true, + .fifo_depth = 0x100, + .interrupts = {0x0, 0xc, 0x4}, + .max_frequency = 0x8f0d180, + .pinctrl_0 = {0x45, 0x46, 0x47, 0x48}, + .pinctrl_names = "default", + .reg = {0xff500000, 0x4000}, + .u_boot_spl_fifo_mode = true, + .vmmc_supply = 0x49, +}; +U_BOOT_DRVINFO(mmc_at_ff500000) = { + .name = "rockchip_rk3288_dw_mshc", + .plat = &dtv_mmc_at_ff500000, + .plat_size = sizeof(dtv_mmc_at_ff500000), + .parent_idx = -1, +}; + +/* + * Node /serial@ff130000 index 3 + * driver ns16550_serial parent None + */ +static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { + .clock_frequency = 0x16e3600, + .clocks = { + {0, {40}}, + {0, {212}},}, + .dma_names = {"tx", "rx"}, + .dmas = {0x10, 0x6, 0x10, 0x7}, + .interrupts = {0x0, 0x39, 0x4}, + .pinctrl_0 = 0x24, + .pinctrl_names = "default", + .reg = {0xff130000, 0x100}, + .reg_io_width = 0x4, + .reg_shift = 0x2, +}; +U_BOOT_DRVINFO(serial_at_ff130000) = { + .name = "ns16550_serial", + .plat = &dtv_serial_at_ff130000, + .plat_size = sizeof(dtv_serial_at_ff130000), + .parent_idx = -1, +}; + +/* Node /spi@ff190000 index 4 */ +static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = { + .clocks = { + {0, {32}}, + {0, {209}},}, + .dma_names = {"tx", "rx"}, + .dmas = {0x10, 0x8, 0x10, 0x9}, + .interrupts = {0x0, 0x31, 0x4}, + .pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f}, + .pinctrl_names = "default", + .reg = {0xff190000, 0x1000}, +}; +U_BOOT_DRVINFO(spi_at_ff190000) = { + .name = "rockchip_rk3328_spi", + .plat = &dtv_spi_at_ff190000, + .plat_size = sizeof(dtv_spi_at_ff190000), + .parent_idx = -1, +}; + +/* + * Node /syscon@ff100000 index 5 + * driver rockchip_rk3328_grf parent None + */ +static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { + .reg = {0xff100000, 0x1000}, +}; +U_BOOT_DRVINFO(syscon_at_ff100000) = { + .name = "rockchip_rk3328_grf", + .plat = &dtv_syscon_at_ff100000, + .plat_size = sizeof(dtv_syscon_at_ff100000), + .parent_idx = -1, +}; + diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h new file mode 100644 index 0000000000..d095831531 --- /dev/null +++ b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h @@ -0,0 +1,55 @@ +/* + * DO NOT MODIFY + * + * Defines the structs used to hold devicetree data. + * This was generated by dtoc from a .dtb (device tree binary) file. + */ + +#include +#include +struct dtd_ns16550_serial { + fdt32_t clock_frequency; + struct phandle_1_arg clocks[2]; + const char * dma_names[2]; + fdt32_t dmas[4]; + fdt32_t interrupts[3]; + fdt32_t pinctrl_0; + const char * pinctrl_names; + fdt64_t reg[2]; + fdt32_t reg_io_width; + fdt32_t reg_shift; +}; +struct dtd_rockchip_rk3288_dw_mshc { + fdt32_t bus_width; + bool cap_sd_highspeed; + struct phandle_1_arg clocks[4]; + bool disable_wp; + fdt32_t fifo_depth; + fdt32_t interrupts[3]; + fdt32_t max_frequency; + fdt32_t pinctrl_0[4]; + const char * pinctrl_names; + fdt64_t reg[2]; + bool u_boot_spl_fifo_mode; + fdt32_t vmmc_supply; +}; +struct dtd_rockchip_rk3328_cru { + fdt64_t reg[2]; + fdt32_t rockchip_grf; +}; +struct dtd_rockchip_rk3328_dmc { + fdt64_t reg[12]; + fdt32_t rockchip_sdram_params[196]; +}; +struct dtd_rockchip_rk3328_grf { + fdt64_t reg[2]; +}; +struct dtd_rockchip_rk3328_spi { + struct phandle_1_arg clocks[2]; + const char * dma_names[2]; + fdt32_t dmas[4]; + fdt32_t interrupts[3]; + fdt32_t pinctrl_0[4]; + const char * pinctrl_names; + fdt64_t reg[2]; +}; From ab641efe698f4412319fcbcfe6ffde64c929cd97 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Tue, 30 May 2023 12:59:07 +0800 Subject: [PATCH 12/16] rockchip: add Orange Pi R1 Plus support Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong. This device is similar to the NanoPi R2S, and has a 16MB SPI NOR (mx25l12805d). The reset button is changed to directly reset the power supply, another detail is that both network ports have independent MAC addresses. Note: booting from SPI is currently unsupported, you have to install the image on a SD card. Signed-off-by: Tianling Shen --- .../armv8/base-files/etc/board.d/01_leds | 3 +- .../armv8/base-files/etc/board.d/02_network | 6 +- .../etc/hotplug.d/net/40-net-smp-affinity | 3 +- target/linux/rockchip/image/armv8.mk | 9 + ...ockchip-rk3328-Add-Orange-Pi-R1-Plus.patch | 407 ++++++++++++++++++ ...ip-Update-LED-properties-for-Orange-.patch | 56 +++ ...ip-add-LED-configuration-to-Orange-P.patch | 24 ++ ...ockchip-rk3328-Add-Orange-Pi-R1-Plus.patch | 407 ++++++++++++++++++ ...ip-Update-LED-properties-for-Orange-.patch | 56 +++ ...ip-add-LED-configuration-to-Orange-P.patch | 24 ++ 10 files changed, 992 insertions(+), 3 deletions(-) create mode 100644 target/linux/rockchip/patches-5.15/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch create mode 100644 target/linux/rockchip/patches-5.15/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch create mode 100644 target/linux/rockchip/patches-5.15/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch create mode 100644 target/linux/rockchip/patches-6.1/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch create mode 100644 target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch create mode 100644 target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds index 2c9206b03e..f0da262a09 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds @@ -10,7 +10,8 @@ board_config_update case $board in friendlyarm,nanopi-r2c|\ friendlyarm,nanopi-r2s|\ -friendlyarm,nanopi-r4s) +friendlyarm,nanopi-r4s|\ +xunlong,orangepi-r1-plus) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1" ;; diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index 16ba01b7e3..f7e0da67b2 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -8,7 +8,8 @@ rockchip_setup_interfaces() case "$board" in friendlyarm,nanopi-r2s|\ - friendlyarm,nanopi-r4s) + friendlyarm,nanopi-r4s|\ + xunlong,orangepi-r1-plus) ucidef_set_interfaces_lan_wan 'eth1' 'eth0' ;; *) @@ -55,6 +56,9 @@ rockchip_setup_macs() wan_mac=$(nanopi_r4s_get_mac wan) lan_mac=$(nanopi_r4s_get_mac lan) ;; + xunlong,orangepi-r1-plus) + wan_mac=$(macaddr_add "$(cat /sys/class/net/eth1/address)" -1) + ;; esac [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index 3d1d99128e..660a7e2866 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -30,7 +30,8 @@ set_interface_core() { case "$(board_name)" in friendlyarm,nanopi-r2c|\ -friendlyarm,nanopi-r2s) +friendlyarm,nanopi-r2s|\ +xunlong,orangepi-r1-plus) set_interface_core 2 "eth0" set_interface_core 4 "eth1" "xhci-hcd:usb3" ;; diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 601ddcbdd6..9a32a07b21 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -60,3 +60,12 @@ define Device/radxa_rock-pi-4a IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata endef TARGET_DEVICES += radxa_rock-pi-4a + +define Device/xunlong_orangepi-r1-plus + DEVICE_VENDOR := Xunlong + DEVICE_MODEL := Orange Pi R1 Plus + SOC := rk3328 + IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := kmod-usb-net-rtl8152 +endef +TARGET_DEVICES += xunlong_orangepi-r1-plus diff --git a/target/linux/rockchip/patches-5.15/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch b/target/linux/rockchip/patches-5.15/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch new file mode 100644 index 0000000000..053a4d0d8e --- /dev/null +++ b/target/linux/rockchip/patches-5.15/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch @@ -0,0 +1,407 @@ +From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sat, 3 Dec 2022 15:41:49 +0800 +Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus + +Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong. + +This device is similar to the NanoPi R2S, and has a 16MB +SPI NOR (mx25l12805d). The reset button is changed to +directly reset the power supply, another detail is that +both network ports have independent MAC addresses. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++ + 2 files changed, 374 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -0,0 +1,373 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Based on rk3328-nanopi-r2s.dts, which is: ++ * Copyright (c) 2020 David Bauer ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include "rk3328.dtsi" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus"; ++ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; ++ ++ aliases { ++ ethernet1 = &rtl8153; ++ mmc0 = &sdmmc; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac_clk: gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; ++ pinctrl-names = "default"; ++ ++ led-0 { ++ function = LED_FUNCTION_LAN; ++ color = ; ++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-1 { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led-2 { ++ function = LED_FUNCTION_WAN; ++ color = ; ++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&sdmmc0m1_pin>; ++ pinctrl-names = "default"; ++ regulator-name = "vcc_sd"; ++ regulator-boot-on; ++ vin-supply = <&vcc_io>; ++ }; ++ ++ vcc_sys: vcc-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vdd_5v_lan: vdd-5v-lan-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&lan_vdd_pin>; ++ pinctrl-names = "default"; ++ regulator-name = "vdd_5v_lan"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&display_subsystem { ++ status = "disabled"; ++}; ++ ++&gmac2io { ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; ++ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; ++ clock_in_out = "input"; ++ phy-handle = <&rtl8211e>; ++ phy-mode = "rgmii"; ++ phy-supply = <&vcc_io>; ++ pinctrl-0 = <&rgmiim1_pins>; ++ pinctrl-names = "default"; ++ snps,aal; ++ rx_delay = <0x18>; ++ tx_delay = <0x24>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rtl8211e: ethernet-phy@1 { ++ reg = <1>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ rk805: pmic@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-0 = <&pmic_int_l>; ++ pinctrl-names = "default"; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_io>; ++ vcc6-supply = <&vcc_sys>; ++ ++ regulators { ++ vdd_log: DCDC_REG1 { ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io: DCDC_REG4 { ++ regulator-name = "vcc_io"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_18: LDO_REG1 { ++ regulator-name = "vcc_18"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc18_emmc: LDO_REG2 { ++ regulator-name = "vcc18_emmc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_10: LDO_REG3 { ++ regulator-name = "vdd_10"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&io_domains { ++ pmuio-supply = <&vcc_io>; ++ vccio1-supply = <&vcc_io>; ++ vccio2-supply = <&vcc18_emmc>; ++ vccio3-supply = <&vcc_io>; ++ vccio4-supply = <&vcc_io>; ++ vccio5-supply = <&vcc_io>; ++ vccio6-supply = <&vcc_io>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gmac2io { ++ eth_phy_reset_pin: eth-phy-reset-pin { ++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ lan { ++ lan_vdd_pin: lan-vdd-pin { ++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; ++ pinctrl-names = "default"; ++ vmmc-supply = <&vcc_sd>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <50000000>; ++ }; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <0>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&u2phy { ++ status = "okay"; ++}; ++ ++&u2phy_host { ++ status = "okay"; ++}; ++ ++&u2phy_otg { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb20_otg { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* Second port is for USB 3.0 */ ++ rtl8153: device@2 { ++ compatible = "usbbda,8153"; ++ reg = <2>; ++ }; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-5.15/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch b/target/linux/rockchip/patches-5.15/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch new file mode 100644 index 0000000000..b1e26d4e3e --- /dev/null +++ b/target/linux/rockchip/patches-5.15/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch @@ -0,0 +1,56 @@ +From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Fri, 19 May 2023 12:10:52 +0800 +Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1 + Plus + +Add OpenWrt's LED aliases for showing system status. +Also replace function/color with legacy label as OpenWrt relys on it +to update LED settings. + +Signed-off-by: Tianling Shen +--- + .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++-------- + 1 file changed, 9 insertions(+), 8 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -17,6 +17,11 @@ + aliases { + ethernet1 = &rtl8153; + mmc0 = &sdmmc; ++ ++ led-boot = &status_led; ++ led-failsafe = &status_led; ++ led-running = &status_led; ++ led-upgrade = &status_led; + }; + + chosen { +@@ -36,22 +41,18 @@ + pinctrl-names = "default"; + + led-0 { +- function = LED_FUNCTION_LAN; +- color = ; + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; ++ label = "green:lan"; + }; + +- led-1 { +- function = LED_FUNCTION_STATUS; +- color = ; ++ status_led: led-1 { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; ++ label = "red:status"; + }; + + led-2 { +- function = LED_FUNCTION_WAN; +- color = ; + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; ++ label = "green:wan"; + }; + }; + diff --git a/target/linux/rockchip/patches-5.15/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch b/target/linux/rockchip/patches-5.15/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch new file mode 100644 index 0000000000..37b59925fc --- /dev/null +++ b/target/linux/rockchip/patches-5.15/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch @@ -0,0 +1,24 @@ +From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Fri, 19 May 2023 12:38:04 +0800 +Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1 + Plus + +Add the correct value for the RTL8153 LED configuration register to +match the blink behavior of the other port on the device. + +Signed-off-by: Tianling Shen +--- + arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -362,6 +362,7 @@ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; ++ realtek,led-data = <0x87>; + }; + }; + diff --git a/target/linux/rockchip/patches-6.1/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch b/target/linux/rockchip/patches-6.1/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch new file mode 100644 index 0000000000..4e48218b89 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch @@ -0,0 +1,407 @@ +From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sat, 3 Dec 2022 15:41:49 +0800 +Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus + +Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong. + +This device is similar to the NanoPi R2S, and has a 16MB +SPI NOR (mx25l12805d). The reset button is changed to +directly reset the power supply, another detail is that +both network ports have independent MAC addresses. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++ + 2 files changed, 374 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -0,0 +1,373 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Based on rk3328-nanopi-r2s.dts, which is: ++ * Copyright (c) 2020 David Bauer ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include "rk3328.dtsi" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus"; ++ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; ++ ++ aliases { ++ ethernet1 = &rtl8153; ++ mmc0 = &sdmmc; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac_clk: gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; ++ pinctrl-names = "default"; ++ ++ led-0 { ++ function = LED_FUNCTION_LAN; ++ color = ; ++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-1 { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led-2 { ++ function = LED_FUNCTION_WAN; ++ color = ; ++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&sdmmc0m1_pin>; ++ pinctrl-names = "default"; ++ regulator-name = "vcc_sd"; ++ regulator-boot-on; ++ vin-supply = <&vcc_io>; ++ }; ++ ++ vcc_sys: vcc-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vdd_5v_lan: vdd-5v-lan-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&lan_vdd_pin>; ++ pinctrl-names = "default"; ++ regulator-name = "vdd_5v_lan"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&display_subsystem { ++ status = "disabled"; ++}; ++ ++&gmac2io { ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; ++ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; ++ clock_in_out = "input"; ++ phy-handle = <&rtl8211e>; ++ phy-mode = "rgmii"; ++ phy-supply = <&vcc_io>; ++ pinctrl-0 = <&rgmiim1_pins>; ++ pinctrl-names = "default"; ++ snps,aal; ++ rx_delay = <0x18>; ++ tx_delay = <0x24>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rtl8211e: ethernet-phy@1 { ++ reg = <1>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ rk805: pmic@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-0 = <&pmic_int_l>; ++ pinctrl-names = "default"; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_io>; ++ vcc6-supply = <&vcc_sys>; ++ ++ regulators { ++ vdd_log: DCDC_REG1 { ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io: DCDC_REG4 { ++ regulator-name = "vcc_io"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_18: LDO_REG1 { ++ regulator-name = "vcc_18"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc18_emmc: LDO_REG2 { ++ regulator-name = "vcc18_emmc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_10: LDO_REG3 { ++ regulator-name = "vdd_10"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&io_domains { ++ pmuio-supply = <&vcc_io>; ++ vccio1-supply = <&vcc_io>; ++ vccio2-supply = <&vcc18_emmc>; ++ vccio3-supply = <&vcc_io>; ++ vccio4-supply = <&vcc_io>; ++ vccio5-supply = <&vcc_io>; ++ vccio6-supply = <&vcc_io>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gmac2io { ++ eth_phy_reset_pin: eth-phy-reset-pin { ++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ lan { ++ lan_vdd_pin: lan-vdd-pin { ++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; ++ pinctrl-names = "default"; ++ vmmc-supply = <&vcc_sd>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <50000000>; ++ }; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <0>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&u2phy { ++ status = "okay"; ++}; ++ ++&u2phy_host { ++ status = "okay"; ++}; ++ ++&u2phy_otg { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb20_otg { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* Second port is for USB 3.0 */ ++ rtl8153: device@2 { ++ compatible = "usbbda,8153"; ++ reg = <2>; ++ }; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch b/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch new file mode 100644 index 0000000000..b1e26d4e3e --- /dev/null +++ b/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch @@ -0,0 +1,56 @@ +From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Fri, 19 May 2023 12:10:52 +0800 +Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1 + Plus + +Add OpenWrt's LED aliases for showing system status. +Also replace function/color with legacy label as OpenWrt relys on it +to update LED settings. + +Signed-off-by: Tianling Shen +--- + .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++-------- + 1 file changed, 9 insertions(+), 8 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -17,6 +17,11 @@ + aliases { + ethernet1 = &rtl8153; + mmc0 = &sdmmc; ++ ++ led-boot = &status_led; ++ led-failsafe = &status_led; ++ led-running = &status_led; ++ led-upgrade = &status_led; + }; + + chosen { +@@ -36,22 +41,18 @@ + pinctrl-names = "default"; + + led-0 { +- function = LED_FUNCTION_LAN; +- color = ; + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; ++ label = "green:lan"; + }; + +- led-1 { +- function = LED_FUNCTION_STATUS; +- color = ; ++ status_led: led-1 { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; ++ label = "red:status"; + }; + + led-2 { +- function = LED_FUNCTION_WAN; +- color = ; + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; ++ label = "green:wan"; + }; + }; + diff --git a/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch b/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch new file mode 100644 index 0000000000..37b59925fc --- /dev/null +++ b/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch @@ -0,0 +1,24 @@ +From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Fri, 19 May 2023 12:38:04 +0800 +Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1 + Plus + +Add the correct value for the RTL8153 LED configuration register to +match the blink behavior of the other port on the device. + +Signed-off-by: Tianling Shen +--- + arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -362,6 +362,7 @@ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; ++ realtek,led-data = <0x87>; + }; + }; + From 37fed89166e6e21c20ef92b36106f7184a0476c6 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Tue, 30 May 2023 12:59:07 +0800 Subject: [PATCH 13/16] uboot-rockchip: add Orange Pi R1 Plus LTS support Add support for the Xunlong Orange Pi R1 Plus LTS. Manually generated of-platdata files to avoid swig dependency. Tested-by: Volkan Yetik Signed-off-by: Tianling Shen --- package/boot/uboot-rockchip/Makefile | 8 + ...Add-support-for-Orange-Pi-R1-Plus-LT.patch | 242 ++++++++++++++++++ .../orangepi-r1-plus-lts-rk3328/dt-decl.h | 24 ++ .../orangepi-r1-plus-lts-rk3328/dt-plat.c | 170 ++++++++++++ .../dt-structs-gen.h | 55 ++++ 5 files changed, 499 insertions(+) create mode 100644 package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch create mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h create mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c create mode 100644 package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 126af6ac54..59b8be84cf 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -52,6 +52,13 @@ define U-Boot/orangepi-r1-plus-rk3328 xunlong_orangepi-r1-plus endef +define U-Boot/orangepi-r1-plus-lts-rk3328 + $(U-Boot/rk3328/Default) + NAME:=Orange Pi R1 Plus LTS + BUILD_DEVICES:= \ + xunlong_orangepi-r1-plus-lts +endef + define U-Boot/roc-cc-rk3328 $(U-Boot/rk3328/Default) NAME:=ROC-RK3328-CC @@ -95,6 +102,7 @@ UBOOT_TARGETS := \ nanopi-r2c-rk3328 \ nanopi-r2s-rk3328 \ orangepi-r1-plus-rk3328 \ + orangepi-r1-plus-lts-rk3328 \ roc-cc-rk3328 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes diff --git a/package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch b/package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch new file mode 100644 index 0000000000..05d569e720 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch @@ -0,0 +1,242 @@ +From 7a9326a96098bc63d2b60538f657c3a533415276 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 20 May 2023 18:52:14 +0800 +Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus LTS + +The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with +the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type +changed from DDR4 to LPDDR3. + +The device tree is taken from kernel v6.4-rc1. + +Signed-off-by: Tianling Shen + +--- + arch/arm/dts/Makefile | 1 + + .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 46 +++++++ + arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 40 ++++++ + board/rockchip/evb_rk3328/MAINTAINERS | 6 + + configs/orangepi-r1-plus-lts-rk3328_defconfig | 114 ++++++++++++++++++ + 5 files changed, 207 insertions(+) + create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts + create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -111,6 +111,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ + rk3328-nanopi-r2c.dtb \ + rk3328-nanopi-r2s.dtb \ + rk3328-orangepi-r1-plus.dtb \ ++ rk3328-orangepi-r1-plus-lts.dtb \ + rk3328-roc-cc.dtb \ + rk3328-rock64.dtb \ + rk3328-rock-pi-e.dtb +--- /dev/null ++++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi +@@ -0,0 +1,46 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd ++ * (C) Copyright 2020 David Bauer ++ */ ++ ++#include "rk3328-u-boot.dtsi" ++#include "rk3328-sdram-lpddr3-666.dtsi" ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; ++ }; ++}; ++ ++&gpio0 { ++ u-boot,dm-spl; ++}; ++ ++&pinctrl { ++ u-boot,dm-spl; ++}; ++ ++&sdmmc0m1_gpio { ++ u-boot,dm-spl; ++}; ++ ++&pcfg_pull_up_4ma { ++ u-boot,dm-spl; ++}; ++ ++/* Need this and all the pinctrl/gpio stuff above to set pinmux */ ++&vcc_sd { ++ u-boot,dm-spl; ++}; ++ ++&gmac2io { ++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++}; ++ ++&spi0 { ++ spi_flash: spiflash@0 { ++ u-boot,dm-pre-reloc; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts +@@ -0,0 +1,40 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2016 Xunlong Software. Co., Ltd. ++ * (http://www.orangepi.org) ++ * ++ * Copyright (c) 2021-2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3328-orangepi-r1-plus.dts" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus LTS"; ++ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; ++}; ++ ++&gmac2io { ++ phy-handle = <&yt8531c>; ++ tx_delay = <0x19>; ++ rx_delay = <0x05>; ++ ++ mdio { ++ /delete-node/ ethernet-phy@1; ++ ++ yt8531c: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ ++ motorcomm,clk-out-frequency-hz = <125000000>; ++ motorcomm,keep-pll-enabled; ++ motorcomm,auto-sleep-disabled; ++ ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <15000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; +--- a/board/rockchip/evb_rk3328/MAINTAINERS ++++ b/board/rockchip/evb_rk3328/MAINTAINERS +@@ -24,6 +24,12 @@ S: Maintained + F: configs/orangepi-r1-plus-rk3328_defconfig + F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi + ++ORANGEPI-R1-PLUS-LTS-RK3328 ++M: Tianling Shen ++S: Maintained ++F: configs/orangepi-r1-plus-lts-rk3328_defconfig ++F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi ++ + ROC-RK3328-CC + M: Loic Devulder + M: Chen-Yu Tsai +--- /dev/null ++++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig +@@ -0,0 +1,98 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO_SUPPORT=y ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_ROCKCHIP_RK3328=y ++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_TPL_LIBCOMMON_SUPPORT=y ++CONFIG_TPL_LIBGENERIC_SUPPORT=y ++CONFIG_SPL_DRIVERS_MISC_SUPPORT=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEBUG_UART_BASE=0xFF130000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYSINFO=y ++CONFIG_DEBUG_UART=y ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 ++# CONFIG_ANDROID_BOOT_IMAGE is not set ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb" ++CONFIG_MISC_INIT_R=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_TPL_SYS_MALLOC_SIMPLE=y ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_I2C_SUPPORT=y ++CONFIG_SPL_POWER_SUPPORT=y ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_TPL_OF_CONTROL=y ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_TPL_OF_PLATDATA=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_TPL_DM=y ++CONFIG_REGMAP=y ++CONFIG_SPL_REGMAP=y ++CONFIG_TPL_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_SYSCON=y ++CONFIG_TPL_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_FASTBOOT_BUF_ADDR=0x800800 ++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=20000000 ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_SPL_RAM=y ++CONFIG_TPL_RAM=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++# CONFIG_TPL_SYSRESET is not set ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_TPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h new file mode 100644 index 0000000000..75795aa6cc --- /dev/null +++ b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h @@ -0,0 +1,24 @@ +/* + * DO NOT MODIFY + * + * Declares externs for all device/uclass instances. + * This was generated by dtoc from a .dtb (device tree binary) file. + */ + +#include +#include + +/* driver declarations - these allow DM_DRIVER_GET() to be used */ +extern U_BOOT_DRIVER(rockchip_rk3328_cru); +extern U_BOOT_DRIVER(rockchip_rk3328_dmc); +extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc); +extern U_BOOT_DRIVER(ns16550_serial); +extern U_BOOT_DRIVER(rockchip_rk3328_spi); +extern U_BOOT_DRIVER(rockchip_rk3328_grf); + +/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */ +extern UCLASS_DRIVER(clk); +extern UCLASS_DRIVER(mmc); +extern UCLASS_DRIVER(ram); +extern UCLASS_DRIVER(serial); +extern UCLASS_DRIVER(syscon); diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c new file mode 100644 index 0000000000..12081b19e0 --- /dev/null +++ b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c @@ -0,0 +1,170 @@ +/* + * DO NOT MODIFY + * + * Declares the U_BOOT_DRIVER() records and platform data. + * This was generated by dtoc from a .dtb (device tree binary) file. + */ + +/* Allow use of U_BOOT_DRVINFO() in this file */ +#define DT_PLAT_C + +#include +#include +#include + +/* + * driver_info declarations, ordered by 'struct driver_info' linker_list idx: + * + * idx driver_info driver + * --- -------------------- -------------------- + * 0: clock_controller_at_ff440000 rockchip_rk3328_cru + * 1: dmc rockchip_rk3328_dmc + * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc + * 3: serial_at_ff130000 ns16550_serial + * 4: spi_at_ff190000 rockchip_rk3328_spi + * 5: syscon_at_ff100000 rockchip_rk3328_grf + * --- -------------------- -------------------- + */ + +/* + * Node /clock-controller@ff440000 index 0 + * driver rockchip_rk3328_cru parent None + */ +static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { + .reg = {0xff440000, 0x1000}, + .rockchip_grf = 0x38, +}; +U_BOOT_DRVINFO(clock_controller_at_ff440000) = { + .name = "rockchip_rk3328_cru", + .plat = &dtv_clock_controller_at_ff440000, + .plat_size = sizeof(dtv_clock_controller_at_ff440000), + .parent_idx = -1, +}; + +/* + * Node /dmc index 1 + * driver rockchip_rk3328_dmc parent None + */ +static struct dtd_rockchip_rk3328_dmc dtv_dmc = { + .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, + 0xff720000, 0x1000, 0xff798000, 0x1000}, + .rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10, + 0x10, 0x10, 0x0, 0x8c48a18a, 0x0, 0x21, 0x482, 0x15, + 0x21a, 0xff, 0x14d, 0x6, 0x1, 0x0, 0x0, 0x0, + 0x43041008, 0x64, 0x140023, 0xd0, 0x220002, 0xd4, 0x10000, 0xd8, + 0x703, 0xdc, 0x830004, 0xe0, 0x10000, 0xe4, 0x70003, 0xf4, + 0xf011f, 0x100, 0x6090b07, 0x104, 0x2020b, 0x108, 0x2030506, 0x10c, + 0x505000, 0x110, 0x3020204, 0x114, 0x1010303, 0x118, 0x2020003, 0x120, + 0x303, 0x138, 0x25, 0x180, 0x3c000f, 0x184, 0x900000, 0x190, + 0x7020000, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0x900090c, 0x244, + 0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0x6, 0x2c, + 0x0, 0x30, 0x3, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79, + 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87, + 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, + 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, + 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, + 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77, + 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78, + 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, + 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x79, 0x9}, +}; +U_BOOT_DRVINFO(dmc) = { + .name = "rockchip_rk3328_dmc", + .plat = &dtv_dmc, + .plat_size = sizeof(dtv_dmc), + .parent_idx = -1, +}; + +/* + * Node /mmc@ff500000 index 2 + * driver rockchip_rk3288_dw_mshc parent None + */ +static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { + .bus_width = 0x4, + .cap_sd_highspeed = true, + .clocks = { + {0, {317}}, + {0, {33}}, + {0, {74}}, + {0, {78}},}, + .disable_wp = true, + .fifo_depth = 0x100, + .interrupts = {0x0, 0xc, 0x4}, + .max_frequency = 0x8f0d180, + .pinctrl_0 = {0x45, 0x46, 0x47, 0x48}, + .pinctrl_names = "default", + .reg = {0xff500000, 0x4000}, + .u_boot_spl_fifo_mode = true, + .vmmc_supply = 0x49, +}; +U_BOOT_DRVINFO(mmc_at_ff500000) = { + .name = "rockchip_rk3288_dw_mshc", + .plat = &dtv_mmc_at_ff500000, + .plat_size = sizeof(dtv_mmc_at_ff500000), + .parent_idx = -1, +}; + +/* + * Node /serial@ff130000 index 3 + * driver ns16550_serial parent None + */ +static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { + .clock_frequency = 0x16e3600, + .clocks = { + {0, {40}}, + {0, {212}},}, + .dma_names = {"tx", "rx"}, + .dmas = {0x10, 0x6, 0x10, 0x7}, + .interrupts = {0x0, 0x39, 0x4}, + .pinctrl_0 = 0x24, + .pinctrl_names = "default", + .reg = {0xff130000, 0x100}, + .reg_io_width = 0x4, + .reg_shift = 0x2, +}; +U_BOOT_DRVINFO(serial_at_ff130000) = { + .name = "ns16550_serial", + .plat = &dtv_serial_at_ff130000, + .plat_size = sizeof(dtv_serial_at_ff130000), + .parent_idx = -1, +}; + +/* Node /spi@ff190000 index 4 */ +static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = { + .clocks = { + {0, {32}}, + {0, {209}},}, + .dma_names = {"tx", "rx"}, + .dmas = {0x10, 0x8, 0x10, 0x9}, + .interrupts = {0x0, 0x31, 0x4}, + .pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f}, + .pinctrl_names = "default", + .reg = {0xff190000, 0x1000}, +}; +U_BOOT_DRVINFO(spi_at_ff190000) = { + .name = "rockchip_rk3328_spi", + .plat = &dtv_spi_at_ff190000, + .plat_size = sizeof(dtv_spi_at_ff190000), + .parent_idx = -1, +}; + +/* + * Node /syscon@ff100000 index 5 + * driver rockchip_rk3328_grf parent None + */ +static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { + .reg = {0xff100000, 0x1000}, +}; +U_BOOT_DRVINFO(syscon_at_ff100000) = { + .name = "rockchip_rk3328_grf", + .plat = &dtv_syscon_at_ff100000, + .plat_size = sizeof(dtv_syscon_at_ff100000), + .parent_idx = -1, +}; + diff --git a/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h new file mode 100644 index 0000000000..d095831531 --- /dev/null +++ b/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h @@ -0,0 +1,55 @@ +/* + * DO NOT MODIFY + * + * Defines the structs used to hold devicetree data. + * This was generated by dtoc from a .dtb (device tree binary) file. + */ + +#include +#include +struct dtd_ns16550_serial { + fdt32_t clock_frequency; + struct phandle_1_arg clocks[2]; + const char * dma_names[2]; + fdt32_t dmas[4]; + fdt32_t interrupts[3]; + fdt32_t pinctrl_0; + const char * pinctrl_names; + fdt64_t reg[2]; + fdt32_t reg_io_width; + fdt32_t reg_shift; +}; +struct dtd_rockchip_rk3288_dw_mshc { + fdt32_t bus_width; + bool cap_sd_highspeed; + struct phandle_1_arg clocks[4]; + bool disable_wp; + fdt32_t fifo_depth; + fdt32_t interrupts[3]; + fdt32_t max_frequency; + fdt32_t pinctrl_0[4]; + const char * pinctrl_names; + fdt64_t reg[2]; + bool u_boot_spl_fifo_mode; + fdt32_t vmmc_supply; +}; +struct dtd_rockchip_rk3328_cru { + fdt64_t reg[2]; + fdt32_t rockchip_grf; +}; +struct dtd_rockchip_rk3328_dmc { + fdt64_t reg[12]; + fdt32_t rockchip_sdram_params[196]; +}; +struct dtd_rockchip_rk3328_grf { + fdt64_t reg[2]; +}; +struct dtd_rockchip_rk3328_spi { + struct phandle_1_arg clocks[2]; + const char * dma_names[2]; + fdt32_t dmas[4]; + fdt32_t interrupts[3]; + fdt32_t pinctrl_0[4]; + const char * pinctrl_names; + fdt64_t reg[2]; +}; From 32d5921b8b5508a99680ecf1626667517c2cbdb8 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Tue, 30 May 2023 12:59:07 +0800 Subject: [PATCH 14/16] rockchip: add Orange Pi R1 Plus LTS support The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise identical to OrangePi R1 Plus. Tested-by: Volkan Yetik Signed-off-by: Tianling Shen --- .../armv8/base-files/etc/board.d/01_leds | 3 +- .../armv8/base-files/etc/board.d/02_network | 6 +- .../etc/hotplug.d/net/40-net-smp-affinity | 3 +- target/linux/rockchip/image/armv8.mk | 9 +++ ...hip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch | 71 +++++++++++++++++++ ...hip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch | 71 +++++++++++++++++++ 6 files changed, 159 insertions(+), 4 deletions(-) create mode 100644 target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch create mode 100644 target/linux/rockchip/patches-6.1/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds index f0da262a09..d82e47cf53 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds @@ -11,7 +11,8 @@ case $board in friendlyarm,nanopi-r2c|\ friendlyarm,nanopi-r2s|\ friendlyarm,nanopi-r4s|\ -xunlong,orangepi-r1-plus) +xunlong,orangepi-r1-plus|\ +xunlong,orangepi-r1-plus-lts) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1" ;; diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index f7e0da67b2..c10e0cbcc9 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -9,7 +9,8 @@ rockchip_setup_interfaces() case "$board" in friendlyarm,nanopi-r2s|\ friendlyarm,nanopi-r4s|\ - xunlong,orangepi-r1-plus) + xunlong,orangepi-r1-plus|\ + xunlong,orangepi-r1-plus-lts) ucidef_set_interfaces_lan_wan 'eth1' 'eth0' ;; *) @@ -56,7 +57,8 @@ rockchip_setup_macs() wan_mac=$(nanopi_r4s_get_mac wan) lan_mac=$(nanopi_r4s_get_mac lan) ;; - xunlong,orangepi-r1-plus) + xunlong,orangepi-r1-plus|\ + xunlong,orangepi-r1-plus-lts) wan_mac=$(macaddr_add "$(cat /sys/class/net/eth1/address)" -1) ;; esac diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index 660a7e2866..bb119b9185 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -31,7 +31,8 @@ set_interface_core() { case "$(board_name)" in friendlyarm,nanopi-r2c|\ friendlyarm,nanopi-r2s|\ -xunlong,orangepi-r1-plus) +xunlong,orangepi-r1-plus|\ +xunlong,orangepi-r1-plus-lts) set_interface_core 2 "eth0" set_interface_core 4 "eth1" "xhci-hcd:usb3" ;; diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 9a32a07b21..063dc6fd64 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -69,3 +69,12 @@ define Device/xunlong_orangepi-r1-plus DEVICE_PACKAGES := kmod-usb-net-rtl8152 endef TARGET_DEVICES += xunlong_orangepi-r1-plus + +define Device/xunlong_orangepi-r1-plus-lts + DEVICE_VENDOR := Xunlong + DEVICE_MODEL := Orange Pi R1 Plus LTS + SOC := rk3328 + IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := kmod-usb-net-rtl8152 +endef +TARGET_DEVICES += xunlong_orangepi-r1-plus-lts diff --git a/target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch new file mode 100644 index 0000000000..cedf28dc79 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch @@ -0,0 +1,71 @@ +From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 25 Mar 2023 15:40:22 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS + +The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with +the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise +identical to OrangePi R1 Plus. + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++ + 2 files changed, 41 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +@@ -0,0 +1,40 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2016 Xunlong Software. Co., Ltd. ++ * (http://www.orangepi.org) ++ * ++ * Copyright (c) 2021-2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3328-orangepi-r1-plus.dts" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus LTS"; ++ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; ++}; ++ ++&gmac2io { ++ phy-handle = <&yt8531c>; ++ tx_delay = <0x19>; ++ rx_delay = <0x05>; ++ ++ mdio { ++ /delete-node/ ethernet-phy@1; ++ ++ yt8531c: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ ++ motorcomm,clk-out-frequency-hz = <125000000>; ++ motorcomm,keep-pll-enabled; ++ motorcomm,auto-sleep-disabled; ++ ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <15000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.1/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-6.1/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch new file mode 100644 index 0000000000..78d3d51a17 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch @@ -0,0 +1,71 @@ +From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 25 Mar 2023 15:40:22 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS + +The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with +the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise +identical to OrangePi R1 Plus. + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++ + 2 files changed, 41 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +@@ -0,0 +1,40 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2016 Xunlong Software. Co., Ltd. ++ * (http://www.orangepi.org) ++ * ++ * Copyright (c) 2021-2023 Tianling Shen ++ */ ++ ++/dts-v1/; ++#include "rk3328-orangepi-r1-plus.dts" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus LTS"; ++ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; ++}; ++ ++&gmac2io { ++ phy-handle = <&yt8531c>; ++ tx_delay = <0x19>; ++ rx_delay = <0x05>; ++ ++ mdio { ++ /delete-node/ ethernet-phy@1; ++ ++ yt8531c: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ ++ motorcomm,clk-out-frequency-hz = <125000000>; ++ motorcomm,keep-pll-enabled; ++ motorcomm,auto-sleep-disabled; ++ ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <15000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; From 5d51079fd064a86119c6f44920e737cf5e25d3a0 Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Sun, 21 May 2023 23:02:17 +0200 Subject: [PATCH 15/16] lantiq: add patches headers This commit adds headers to the patches, so they can be applied with the git am command. Signed-off-by: Aleksander Jan Bajkowski --- .../patches-5.15/0101-find_active_root.patch | 10 ++++ .../0151-lantiq-ifxmips_pcie-use-of.patch | 34 +++++++---- .../lantiq/patches-5.15/0152-lantiq-VPE.patch | 57 ++++++++++++------- .../0154-lantiq-pci-bar11mask-fix.patch | 10 ++++ .../patches-5.15/0155-lantiq-VPE-nosmp.patch | 10 ++++ .../0160-owrt-lantiq-multiple-flash.patch | 10 ++++ ...-cmdset-0001-disable-buffered-writes.patch | 10 ++++ ...add-gphy-clk-src-device-tree-binding.patch | 10 ++++ .../0701-NET-lantiq-etop-of-mido.patch | 10 ++++ 9 files changed, 129 insertions(+), 32 deletions(-) diff --git a/target/linux/lantiq/patches-5.15/0101-find_active_root.patch b/target/linux/lantiq/patches-5.15/0101-find_active_root.patch index 925ac9dbba..14dc83f1f7 100644 --- a/target/linux/lantiq/patches-5.15/0101-find_active_root.patch +++ b/target/linux/lantiq/patches-5.15/0101-find_active_root.patch @@ -1,3 +1,13 @@ +From 2c82524000cca691c89c9fda251b55ef04eabcb6 Mon Sep 17 00:00:00 2001 +From: Mathias Kresin +Date: Mon, 2 May 2016 18:50:00 +0000 +Subject: [PATCH] find active root + +Signed-off-by: Mathias Kresin +--- + drivers/mtd/parsers/ofpart_core.c | 49 ++++++++++++++++++++++++++++++- + 1 file changed, 48 insertions(+), 1 deletion(-) + --- a/drivers/mtd/parsers/ofpart_core.c +++ b/drivers/mtd/parsers/ofpart_core.c @@ -38,6 +38,38 @@ static bool node_has_compatible(struct d diff --git a/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch index 10633199e6..0b99b91bd9 100644 --- a/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch +++ b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch @@ -1,3 +1,26 @@ +From 1d1885f4a7abd7272f47b835b03d8662fb981d19 Mon Sep 17 00:00:00 2001 +From: Eddi De Pieri +Date: Tue, 14 Oct 2014 11:04:00 +0000 +Subject: [PATCH] MIPS: lantiq: ifxmips_pcie: use of + +Signed-off-by: Eddi De Pieri +--- + arch/mips/pci/Makefile | 2 +- + arch/mips/pci/ifxmips_pcie.c | 151 +++++++++++++++++++++++++++---- + arch/mips/pci/ifxmips_pcie_vr9.h | 105 --------------------- + 3 files changed, 133 insertions(+), 125 deletions(-) + +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -43,7 +43,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o + obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o + obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o +-obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o ++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie.o fixup-lantiq-pcie.o + obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o + obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o + obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o --- a/arch/mips/pci/ifxmips_pcie.c +++ b/arch/mips/pci/ifxmips_pcie.c @@ -16,8 +16,15 @@ @@ -374,14 +397,3 @@ static inline void pcie_core_pmu_setup(int pcie_port) { struct clk *clk; ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -43,7 +43,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o - obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o - obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o - obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o --obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o -+obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie.o fixup-lantiq-pcie.o - obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o - obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o - obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o diff --git a/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch index 4986194548..bf2962a3ff 100644 --- a/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch +++ b/target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch @@ -1,3 +1,18 @@ +From 4d48a3d1ef6f8d036bd926e3c1f70b56fcc679b2 Mon Sep 17 00:00:00 2001 +From: Stefan Koch +Date: Thu, 20 Oct 2016 21:32:00 +0200 +Subject: [PATCH] lantiq: vpe + +Signed-off-by: Stefan Koch +--- + arch/mips/Kconfig | 6 ++++ + arch/mips/include/asm/mipsmtregs.h | 5 ++++ + arch/mips/include/asm/vpe.h | 9 ++++++ + arch/mips/kernel/vpe-mt.c | 47 ++++++++++++++++++++++++++++++ + arch/mips/kernel/vpe.c | 35 ++++++++++++++++++++++ + arch/mips/lantiq/prom.c | 4 +++ + 6 files changed, 106 insertions(+) + --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2429,6 +2429,12 @@ config MIPS_VPE_LOADER @@ -13,6 +28,27 @@ config MIPS_VPE_LOADER_CMP bool default "y" +--- a/arch/mips/include/asm/mipsmtregs.h ++++ b/arch/mips/include/asm/mipsmtregs.h +@@ -32,6 +32,9 @@ + #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) + #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) + ++#define read_c0_vpeopt() __read_32bit_c0_register($1, 7) ++#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val) ++ + #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) + #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) + +@@ -378,6 +381,8 @@ do { \ + #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) + #define read_vpe_c0_vpeconf1() mftc0(1, 3) + #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) ++#define read_vpe_c0_vpeopt() mftc0(1, 7) ++#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val) + #define read_vpe_c0_count() mftc0(9, 0) + #define write_vpe_c0_count(val) mttc0(9, 0, val) + #define read_vpe_c0_status() mftc0(12, 0) --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -124,4 +124,13 @@ void cleanup_tc(struct tc *tc); @@ -157,24 +193,3 @@ int ltq_soc_type(void) { ---- a/arch/mips/include/asm/mipsmtregs.h -+++ b/arch/mips/include/asm/mipsmtregs.h -@@ -32,6 +32,9 @@ - #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) - #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) - -+#define read_c0_vpeopt() __read_32bit_c0_register($1, 7) -+#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val) -+ - #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) - #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) - -@@ -378,6 +381,8 @@ do { \ - #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) - #define read_vpe_c0_vpeconf1() mftc0(1, 3) - #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) -+#define read_vpe_c0_vpeopt() mftc0(1, 7) -+#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val) - #define read_vpe_c0_count() mftc0(9, 0) - #define write_vpe_c0_count(val) mttc0(9, 0, val) - #define read_vpe_c0_status() mftc0(12, 0) diff --git a/target/linux/lantiq/patches-5.15/0154-lantiq-pci-bar11mask-fix.patch b/target/linux/lantiq/patches-5.15/0154-lantiq-pci-bar11mask-fix.patch index d6556d115d..9214f786d7 100644 --- a/target/linux/lantiq/patches-5.15/0154-lantiq-pci-bar11mask-fix.patch +++ b/target/linux/lantiq/patches-5.15/0154-lantiq-pci-bar11mask-fix.patch @@ -1,3 +1,13 @@ +From 3c92a781de062064e36b867c0ab22f9aba48f3d3 Mon Sep 17 00:00:00 2001 +From: Eddi De Pieri +Date: Tue, 8 Nov 2016 17:38:00 +0100 +Subject: [PATCH] lantiq: pci: bar11mask fix + +Signed-off-by: Eddi De Pieri +--- + arch/mips/pci/pci-lantiq.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -59,6 +59,8 @@ diff --git a/target/linux/lantiq/patches-5.15/0155-lantiq-VPE-nosmp.patch b/target/linux/lantiq/patches-5.15/0155-lantiq-VPE-nosmp.patch index 898c2d4821..6562dc8bda 100644 --- a/target/linux/lantiq/patches-5.15/0155-lantiq-VPE-nosmp.patch +++ b/target/linux/lantiq/patches-5.15/0155-lantiq-VPE-nosmp.patch @@ -1,3 +1,13 @@ +From 07ce9e9bc4dcd5ac4728e587901112eef95bbe7b Mon Sep 17 00:00:00 2001 +From: Stefan Koch +Date: Mon, 13 Mar 2017 23:42:00 +0100 +Subject: [PATCH] lantiq: vpe nosmp + +Signed-off-by: Stefan Koch +--- + arch/mips/kernel/vpe-mt.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + --- a/arch/mips/kernel/vpe-mt.c +++ b/arch/mips/kernel/vpe-mt.c @@ -132,7 +132,10 @@ int vpe_run(struct vpe *v) diff --git a/target/linux/lantiq/patches-5.15/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-5.15/0160-owrt-lantiq-multiple-flash.patch index 796220b2bc..a83325c094 100644 --- a/target/linux/lantiq/patches-5.15/0160-owrt-lantiq-multiple-flash.patch +++ b/target/linux/lantiq/patches-5.15/0160-owrt-lantiq-multiple-flash.patch @@ -1,3 +1,13 @@ +From ebaae1cd68cd79c7eee67c9c5c0fa45809e84525 Mon Sep 17 00:00:00 2001 +From: Maikel Bloemendal +Date: Fri, 14 Nov 2014 17:06:00 +0000 +Subject: [PATCH] owrt: lantiq: multiple flash + +Signed-off-by: Maikel Bloemendal +--- + drivers/mtd/maps/lantiq-flash.c | 168 +++++++++++++++++++++----------- + 1 file changed, 109 insertions(+), 59 deletions(-) + --- a/drivers/mtd/maps/lantiq-flash.c +++ b/drivers/mtd/maps/lantiq-flash.c @@ -17,6 +17,7 @@ diff --git a/target/linux/lantiq/patches-5.15/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-5.15/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch index d153c521d3..f62d167078 100644 --- a/target/linux/lantiq/patches-5.15/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch +++ b/target/linux/lantiq/patches-5.15/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch @@ -1,3 +1,13 @@ +From 5e93c85ac3e5626d1aa7e7f9c0a008b2a4224f04 Mon Sep 17 00:00:00 2001 +From: Matti Laakso +Date: Sat, 14 Feb 2015 20:48:00 +0000 +Subject: [PATCH] MTD: cfi_cmdset_0001: disable buffered writes + +Signed-off-by: Matti Laakso +--- + drivers/mtd/chips/cfi_cmdset_0001.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + --- a/drivers/mtd/chips/cfi_cmdset_0001.c +++ b/drivers/mtd/chips/cfi_cmdset_0001.c @@ -39,7 +39,7 @@ diff --git a/target/linux/lantiq/patches-5.15/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-5.15/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch index 92c4b56493..6dacba56d5 100644 --- a/target/linux/lantiq/patches-5.15/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch +++ b/target/linux/lantiq/patches-5.15/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch @@ -1,3 +1,13 @@ +From 5502ef9d40ab20b2ac683660d1565a7c4968bcc8 Mon Sep 17 00:00:00 2001 +From: Mathias Kresin +Date: Mon, 2 May 2016 18:50:00 +0000 +Subject: [PATCH] xrx200: add gphy clk src device tree binding + +Signed-off-by: Mathias Kresin +--- + arch/mips/lantiq/xway/sysctrl.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -440,6 +440,20 @@ static void clkdev_add_clkout(void) diff --git a/target/linux/lantiq/patches-5.15/0701-NET-lantiq-etop-of-mido.patch b/target/linux/lantiq/patches-5.15/0701-NET-lantiq-etop-of-mido.patch index 2cc541ae3c..7e49b47e02 100644 --- a/target/linux/lantiq/patches-5.15/0701-NET-lantiq-etop-of-mido.patch +++ b/target/linux/lantiq/patches-5.15/0701-NET-lantiq-etop-of-mido.patch @@ -1,3 +1,13 @@ +From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 +From: Johann Neuhauser +Date: Thu, 17 May 2018 19:12:35 +0200 +Subject: [PATCH] net: lantiq_etop: of mdio + +Signed-off-by: Johann Neuhauser +--- + drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- + 1 file changed, 389 insertions(+), 166 deletions(-) + --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -30,6 +30,7 @@ From 4c5a9da8699a7982b8f03b28561f955d9d1313f1 Mon Sep 17 00:00:00 2001 From: Linhui Liu Date: Sat, 27 May 2023 13:13:25 +0800 Subject: [PATCH 16/16] selinux-policy: update to 1.2.5 30d503a uci jsonfilter: pipe and leak e13cb64 rpcd leds 144781f jsonfilter, luci, ubus 1210762 rpcd and all agents get fd's leaked ab9227c rpcd 2f99e0e luci rpcd b43aaf3 rpcd (enable/disable services) luci peeraddr f20f03e rpcd 7bc74f6 rpcd reads all subj state and luci-bwc leaks 9634b17 adds inotify perms to anon_inode 3d3c17c adds bare anon_inode (linux 5.15) 7104b20 dnsmasq and luci 0de2c66 luci,rpcd, ucode, wpad 14f5cf9 luci and ucode e3ce84c rpcd, ucode and cgiio loose ends 96a2401 misc updates 9fe0490 initscript: remove redundant rules 71bd77e allow all init scripts to log to logd f697331 sandbox: make ttydev handling more robust a471877 simplify pty tty console access f738984 sandbox: also remove TIOSCTI from all ttydevs Signed-off-by: Linhui Liu --- package/libs/libselinux/Makefile | 2 +- package/system/selinux-policy/Makefile | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/package/libs/libselinux/Makefile b/package/libs/libselinux/Makefile index db2221d7e3..816e09f30c 100644 --- a/package/libs/libselinux/Makefile +++ b/package/libs/libselinux/Makefile @@ -103,7 +103,7 @@ endef $(foreach a,$(LIBSELINUX_UTILS),$(eval $(call GenUtilPkg,libselinux-$(a),$(a)))) # Needed to link libselinux utilities, which link against -# libselinux.so, which indirectly depends on libpcre.so, installed in +# libselinux.so, which indirectly depends on libpcre2.so, installed in # $(STAGING_DIR_HOSTPKG). HOST_LDFLAGS += -Wl,-rpath="$(STAGING_DIR_HOSTPKG)/lib" diff --git a/package/system/selinux-policy/Makefile b/package/system/selinux-policy/Makefile index bcf6b4a3c2..8e36b267bb 100644 --- a/package/system/selinux-policy/Makefile +++ b/package/system/selinux-policy/Makefile @@ -8,8 +8,8 @@ include $(TOPDIR)/rules.mk PKG_NAME:=selinux-policy PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://git.defensec.nl/selinux-policy.git -PKG_VERSION:=1.2.3 -PKG_MIRROR_HASH:=ff1ddca168a6631aeac34352657f424bc4acf5d50b8aa7ff8dfa8c9663ba8538 +PKG_VERSION:=1.2.5 +PKG_MIRROR_HASH:=81ac6e31d2f1febddbe594f3578a9c40444fc0e349075ab6abd3d3ee014a988e PKG_SOURCE_VERSION:=v$(PKG_VERSION) PKG_BUILD_DEPENDS:=secilc/host policycoreutils/host