Merge Official Source

2020-07-16 20:01:33 +08:00 · 2020-07-16 20:01:33 +08:00 · fc39331fd8
commit fc39331fd8
parent 5cfcdc8c82 ed087cba8a
83 changed files with 2759 additions and 333 deletions
--- a/package/base-files/files/lib/upgrade/nand.sh
+++ b/package/base-files/files/lib/upgrade/nand.sh
@ -231,7 +231,7 @@ nand_upgrade_ubinized() {

 # Write the UBIFS image to UBI volume
 nand_upgrade_ubifs() {
-	local rootfs_length=`(cat $1 | wc -c) 2> /dev/null`
+	local rootfs_length=$( (cat $1 | wc -c) 2> /dev/null)

 	nand_upgrade_prepare_ubi "$rootfs_length" "ubifs" "0" "0"

@ -249,8 +249,8 @@ nand_upgrade_tar() {
 	local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
 	board_dir=${board_dir%/}

-	local kernel_length=`(tar xf $tar_file ${board_dir}/kernel -O | wc -c) 2> /dev/null`
-	local rootfs_length=`(tar xf $tar_file ${board_dir}/root -O | wc -c) 2> /dev/null`
+	local kernel_length=$( (tar xf $tar_file ${board_dir}/kernel -O | wc -c) 2> /dev/null)
+	local rootfs_length=$( (tar xf $tar_file ${board_dir}/root -O | wc -c) 2> /dev/null)

 	local rootfs_type="$(identify_tar "$tar_file" ${board_dir}/root)"

@ -307,7 +307,7 @@ nand_do_upgrade() {
 nand_do_platform_check() {
 	local board_name="$1"
 	local tar_file="$2"
-	local control_length=`(tar xf $tar_file sysupgrade-$board_name/CONTROL -O | wc -c) 2> /dev/null`
+	local control_length=$( (tar xf $tar_file sysupgrade-$board_name/CONTROL -O | wc -c) 2> /dev/null)
 	local file_type="$(identify $2)"

 	[ "$control_length" = 0 -a "$file_type" != "ubi" -a "$file_type" != "ubifs" ] && {
--- a/package/boot/uboot-envtools/files/ramips
+++ b/package/boot/uboot-envtools/files/ramips
@ -33,6 +33,7 @@ xiaomi,miwifi-nano|\
 zbtlink,zbt-wg2626)
 	ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x1000" "0x10000"
 	;;
+linksys,ea7300-v1|\
 linksys,ea7500-v2|\
 xiaomi,mi-router-ac2100|\
 xiaomi,mir3p|\
--- a/package/kernel/om-watchdog/Makefile
+++ b/package/kernel/om-watchdog/Makefile
@ -9,7 +9,6 @@ include $(TOPDIR)/rules.mk

 PKG_NAME:=om-watchdog
 PKG_RELEASE:=2
-PKG_VERSION:=1

 include $(INCLUDE_DIR)/package.mk

--- a/package/kernel/trelay/Makefile
+++ b/package/kernel/trelay/Makefile
@ -9,7 +9,6 @@ include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk

 PKG_NAME:=trelay
-PKG_VERSION:=0.1
 PKG_RELEASE:=2

 include $(INCLUDE_DIR)/package.mk
--- a/package/network/config/gre/Makefile
+++ b/package/network/config/gre/Makefile
@ -8,7 +8,6 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=gre
-PKG_VERSION:=1
 PKG_RELEASE:=12
 PKG_LICENSE:=GPL-2.0

--- a/package/network/config/ipip/Makefile
+++ b/package/network/config/ipip/Makefile
@ -8,7 +8,6 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=ipip
-PKG_VERSION:=1
 PKG_RELEASE:=3
 PKG_LICENSE:=GPL-2.0

--- a/package/network/config/vti/Makefile
+++ b/package/network/config/vti/Makefile
@ -8,7 +8,6 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=vti
-PKG_VERSION:=1
 PKG_RELEASE:=3
 PKG_LICENSE:=GPL-2.0

--- a/package/network/config/vxlan/Makefile
+++ b/package/network/config/vxlan/Makefile
@ -1,7 +1,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=vxlan
-PKG_VERSION:=2
+PKG_RELEASE:=3
 PKG_LICENSE:=GPL-2.0

 include $(INCLUDE_DIR)/package.mk
--- a/package/network/config/vxlan/files/vxlan.sh
+++ b/package/network/config/vxlan/files/vxlan.sh
@ -129,6 +129,8 @@ vxlan_generic_init_config() {
 	proto_config_add_int "ttl"
 	proto_config_add_int "tos"
 	proto_config_add_int "mtu"
+	proto_config_add_boolean "rxcsum"
+	proto_config_add_boolean "txcsum"
 	proto_config_add_string "macaddr"
 }

--- a/package/network/config/xfrm/Makefile
+++ b/package/network/config/xfrm/Makefile
@ -2,7 +2,6 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=xfrm
-PKG_VERSION:=1
 PKG_RELEASE:=2
 PKG_LICENSE:=GPL-2.0

--- a/package/network/ipv6/464xlat/Makefile
+++ b/package/network/ipv6/464xlat/Makefile
@ -1,7 +1,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=464xlat
-PKG_VERSION:=12
+PKG_RELEASE:=12

 PKG_SOURCE_DATE:=2018-01-16
 PKG_MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>
--- a/package/network/ipv6/6in4/Makefile
+++ b/package/network/ipv6/6in4/Makefile
@ -8,8 +8,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=6in4
-PKG_VERSION:=25
-PKG_RELEASE:=1
+PKG_RELEASE:=26
 PKG_LICENSE:=GPL-2.0

 include $(INCLUDE_DIR)/package.mk
--- a/package/network/ipv6/6rd/Makefile
+++ b/package/network/ipv6/6rd/Makefile
@ -8,8 +8,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=6rd
-PKG_VERSION:=9
-PKG_RELEASE:=4
+PKG_RELEASE:=10
 PKG_LICENSE:=GPL-2.0

 include $(INCLUDE_DIR)/package.mk
--- a/package/network/ipv6/6to4/Makefile
+++ b/package/network/ipv6/6to4/Makefile
@ -8,8 +8,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=6to4
-PKG_VERSION:=12
-PKG_RELEASE:=2
+PKG_RELEASE:=13
 PKG_LICENSE:=GPL-2.0

 include $(INCLUDE_DIR)/package.mk
--- a/package/network/ipv6/ds-lite/Makefile
+++ b/package/network/ipv6/ds-lite/Makefile
@ -8,8 +8,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=ds-lite
-PKG_VERSION:=7
-PKG_RELEASE:=4
+PKG_RELEASE:=8
 PKG_LICENSE:=GPL-2.0

 include $(INCLUDE_DIR)/package.mk
--- a/package/network/ipv6/map/Makefile
+++ b/package/network/ipv6/map/Makefile
@ -8,8 +8,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=map
-PKG_VERSION:=4
-PKG_RELEASE:=13
+PKG_RELEASE:=5
 PKG_LICENSE:=GPL-2.0

 include $(INCLUDE_DIR)/package.mk
--- a/package/network/utils/iproute2/Makefile
+++ b/package/network/utils/iproute2/Makefile
@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk

 PKG_NAME:=iproute2
 PKG_VERSION:=5.7.0
-PKG_RELEASE:=1
+PKG_RELEASE:=2

 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@KERNEL/linux/utils/net/iproute2
--- a/package/network/utils/iproute2/patches/002-configure-support-ipset-v7.patch
+++ b/package/network/utils/iproute2/patches/002-configure-support-ipset-v7.patch
@ -0,0 +1,32 @@
+From 650591a7a70cd79d826fcdc579a20c168c987cf2 Mon Sep 17 00:00:00 2001
+From: Tony Ambardar <tony.ambardar@gmail.com>
+Date: Tue, 7 Jul 2020 00:58:33 -0700
+Subject: [PATCH] configure: support ipset version 7 with kernel version 5
+
+The configure script checks for ipset v6 availability but doesn't test
+for v7, which is backward compatible and used on kernel v5.x systems.
+Update the script to test for both ipset versions. Without this change,
+the tc ematch function em_ipset will be disabled.
+
+Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>
+Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
+---
+ configure | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/configure b/configure
+index f415bf49..307912aa 100755
+--- a/configure
+++ b/configure
+@@ -208,7 +208,7 @@ typedef unsigned short ip_set_id_t;
+ #include <linux/netfilter/xt_set.h>
+ 
+ struct xt_set_info info;
+-#if IPSET_PROTOCOL == 6
+#if IPSET_PROTOCOL == 6 || IPSET_PROTOCOL == 7
+ int main(void)
+ {
+ 	return IPSET_MAXNAMELEN;
+-- 
+2.17.1
+
--- a/package/network/utils/iproute2/patches/175-reduce-dynamic-syms.patch
+++ b/package/network/utils/iproute2/patches/175-reduce-dynamic-syms.patch
@ -39,6 +39,6 @@
 +	for s in `grep -B 3 '\<dlsym' $$files | sed -n '/snprintf/{s:.*"\([^"]*\)".*:\1:;s:%s::;p}'` ; do \
 +		sed -n '/'$$s'[^ ]* =/{s:.* \([^ ]*'$$s'[^ ]*\) .*:\1;:;p}' $$files ; \
 +	done >> $@ ; \
-+	echo "show_stats; print_tm; parse_rtattr; get_u32; matches; addattr_l; addattr_nest; addattr_nest_end; };" >> $@
+	echo "show_stats; print_nl; print_tm; parse_rtattr; parse_rtattr_flags; get_u32; matches; addattr_l; addattr_nest; addattr_nest_end; };" >> $@
 +
 endif
--- a/package/network/utils/rssileds/Makefile
+++ b/package/network/utils/rssileds/Makefile
@ -8,8 +8,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=rssileds
-PKG_VERSION:=0.2
-PKG_RELEASE:=2
+PKG_RELEASE:=3
 PKG_LICNESE:=GPL-2.0+

 include $(INCLUDE_DIR)/package.mk
--- a/package/system/procd/Makefile
+++ b/package/system/procd/Makefile
@ -12,9 +12,9 @@ PKG_RELEASE:=3

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/procd.git
-PKG_SOURCE_DATE:=2020-07-13
-PKG_SOURCE_VERSION:=dacab12b301085eac00e84a94e42096de70886e8
-PKG_MIRROR_HASH:=e9c49884ea1dd6554ce057c8ca7fb23bc980939b92e11f43d37b930c29f63dbd
+PKG_SOURCE_DATE:=2020-07-14
+PKG_SOURCE_VERSION:=b2230e4ff28b29472d0a232fee5d9f4168390b52
+PKG_MIRROR_HASH:=67dd91d469a2e996a6b350575cfc0accedcf9ac948feaeee0d665199820bb6b0
 CMAKE_INSTALL:=1

 PKG_LICENSE:=GPL-2.0
--- a/package/system/procd/files/procd.sh
+++ b/package/system/procd/files/procd.sh
@ -247,7 +247,7 @@ _procd_set_param() {
 		env|data|limits)
 			_procd_add_table "$type" "$@"
 		;;
-		command|netdev|file|respawn|watch)
+		command|netdev|file|respawn|watch|watchdog)
 			_procd_add_array "$type" "$@"
 		;;
 		error)
@ -378,7 +378,7 @@ _procd_append_param() {
 		env|data|limits)
 			_procd_add_table_data "$@"
 		;;
-		command|netdev|file|respawn|watch)
+		command|netdev|file|respawn|watch|watchdog)
 			_procd_add_array_data "$@"
 		;;
 		error)
--- a/package/system/urandom-seed/Makefile
+++ b/package/system/urandom-seed/Makefile
@ -1,7 +1,6 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=urandom-seed
-PKG_VERSION:=1.0
 PKG_RELEASE:=2
 PKG_LICENSE:=GPL-2.0-only

--- a/package/system/zram-swap/Makefile
+++ b/package/system/zram-swap/Makefile
@ -8,8 +8,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=zram-swap
-PKG_VERSION:=1.1
-PKG_RELEASE:=4
+PKG_RELEASE:=5

 PKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME)

--- a/package/utils/ravpower-mcu/Makefile
+++ b/package/utils/ravpower-mcu/Makefile
@ -1,7 +1,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=ravpower-mcu
-PKG_RELEASE:=1
+PKG_RELEASE:=2

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=https://github.com/blocktrron/ravpower-mcu.git
@ -17,7 +17,6 @@ define Package/ravpower-mcu
  SECTION:=utils
  CATEGORY:=Utilities
  TITLE:=Utility to control the RAVPower RP-WD009 PMIC
-  DEPENDS:=@TARGET_ramips_mt76x8
  URL:=https://github.com/blocktrron/ravpower-mcu/
 endef

--- a/scripts/json_overview_image_info.py
+++ b/scripts/json_overview_image_info.py
@ -38,7 +38,7 @@ if output:
            "make",
            "--no-print-directory",
            "-C",
-            f"target/linux/{output['target'].split('/')[0]}",
+            "target/linux/{}".format(output['target'].split('/')[0]),
            "val.DEFAULT_PACKAGES",
            "val.ARCH_PACKAGES",
        ],
--- a/target/linux/ath79/dts/ar7161_ubnt_routerstation.dts
+++ b/target/linux/ath79/dts/ar7161_ubnt_routerstation.dts
@ -5,7 +5,7 @@

 / {
 	compatible = "ubnt,routerstation", "qca,ar7161";
-	model = "Ubiquiti Networks RouterStation";
+	model = "Ubiquiti RouterStation";
 };

 &eth0 {
--- a/target/linux/ath79/dts/ar7240_ubnt_bullet-m-ar7240.dts
+++ b/target/linux/ath79/dts/ar7240_ubnt_bullet-m-ar7240.dts
@ -7,7 +7,7 @@

 / {
 	compatible = "ubnt,bullet-m-ar7240", "ubnt,xm", "qca,ar7240";
-	model = "Ubiquiti Bullet M XM (AR7240)";
+	model = "Ubiquiti Bullet M (XM AR7240)";
 };

 &eth0 {
--- a/target/linux/ath79/dts/ar7241_ubnt_airrouter.dts
+++ b/target/linux/ath79/dts/ar7241_ubnt_airrouter.dts
@ -6,7 +6,7 @@

 / {
 	compatible = "ubnt,airrouter", "ubnt,xm", "qca,ar7241";
-	model = "Ubiquiti AirRouter";
+	model = "Ubiquiti AirRouter (XM)";

 	aliases {
 		led-boot = &led_globe;
--- a/target/linux/ath79/dts/ar7241_ubnt_bullet-m-ar7241.dts
+++ b/target/linux/ath79/dts/ar7241_ubnt_bullet-m-ar7241.dts
@ -7,7 +7,7 @@

 / {
 	compatible = "ubnt,bullet-m-ar7241", "ubnt,xm", "qca,ar7241";
-	model = "Ubiquiti Bullet M XM (AR7241)";
+	model = "Ubiquiti Bullet M (XM AR7241)";
 };

 &eth1 {
--- a/target/linux/ath79/dts/ar7241_ubnt_nanobridge-m.dts
+++ b/target/linux/ath79/dts/ar7241_ubnt_nanobridge-m.dts
@ -7,7 +7,7 @@

 / {
 	compatible = "ubnt,nanobridge-m", "ubnt,xm", "qca,ar7241";
-	model = "Ubiquiti NanoBridge M";
+	model = "Ubiquiti NanoBridge M (XM)";
 };

 &eth1 {
--- a/target/linux/ath79/dts/ar7241_ubnt_nanostation-loco-m.dts
+++ b/target/linux/ath79/dts/ar7241_ubnt_nanostation-loco-m.dts
@ -7,7 +7,7 @@

 / {
 	compatible = "ubnt,nanostation-loco-m", "ubnt,xm", "qca,ar7241";
-	model = "Ubiquiti Nanostation Loco M";
+	model = "Ubiquiti Nanostation Loco M (XM)";
 };

 &eth1 {
--- a/target/linux/ath79/dts/ar7241_ubnt_nanostation-m.dts
+++ b/target/linux/ath79/dts/ar7241_ubnt_nanostation-m.dts
@ -7,5 +7,5 @@

 / {
 	compatible = "ubnt,nanostation-m", "ubnt,xm", "qca,ar7241";
-	model = "Ubiquiti Nanostation M";
+	model = "Ubiquiti Nanostation M (XM)";
 };
--- a/target/linux/ath79/dts/ar7241_ubnt_picostation-m.dts
+++ b/target/linux/ath79/dts/ar7241_ubnt_picostation-m.dts
@ -7,7 +7,7 @@

 / {
 	compatible = "ubnt,picostation-m", "ubnt,xm", "qca,ar7241";
-	model = "Ubiquiti Picostation M";
+	model = "Ubiquiti Picostation M (XM)";
 };

 &eth1 {
--- a/target/linux/ath79/dts/ar7241_ubnt_powerbridge-m.dts
+++ b/target/linux/ath79/dts/ar7241_ubnt_powerbridge-m.dts
@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "ar7241.dtsi"
+#include "ar724x_ubnt_xm.dtsi"
+#include "ar724x_ubnt_xm_outdoor.dtsi"
+
+/ {
+	compatible = "ubnt,powerbridge-m", "ubnt,xm", "qca,ar7241";
+	model = "Ubiquiti PowerBridge M (XM)";
+};
+
+&eth1 {
+	compatible = "syscon", "simple-mfd";
+};
--- a/target/linux/ath79/dts/ar7241_ubnt_rocket-m.dts
+++ b/target/linux/ath79/dts/ar7241_ubnt_rocket-m.dts
@ -7,7 +7,7 @@

 / {
 	compatible = "ubnt,rocket-m", "ubnt,xm", "qca,ar7241";
-	model = "Ubiquiti Rocket M";
+	model = "Ubiquiti Rocket M (XM)";
 };

 &eth1 {
--- a/target/linux/ath79/dts/ar7241_ubnt_unifi.dts
+++ b/target/linux/ath79/dts/ar7241_ubnt_unifi.dts
@ -8,7 +8,7 @@

 / {
 	compatible = "ubnt,unifi", "qca,ar7241";
-	model = "Ubiquiti UniFi AP";
+	model = "Ubiquiti UniFi";

 	aliases {
 		led-boot = &led_dome_green;
--- a/target/linux/ath79/dts/ar9342_ubnt_lap-120.dts
+++ b/target/linux/ath79/dts/ar9342_ubnt_lap-120.dts
@ -13,7 +13,6 @@

 	phy-mask = <4>;
 	phy4: ethernet-phy@4 {
-		phy-mode = "rgmii";
 		reg = <4>;
 	};
 };
@ -22,11 +21,11 @@
 	status = "okay";

 	/* default for ar934x, except for 1000M and 10M */
-	pll-data = <0x06000000 0x00000101 0x00001313>;
+	pll-data = <0x02000000 0x00000101 0x00001313>;

 	mtd-mac-address = <&art 0x0>;

-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-handle = <&phy4>;

 	gmac-config {
--- a/target/linux/ath79/dts/qca9563_ubnt_unifiac-lite.dts
+++ b/target/linux/ath79/dts/qca9563_ubnt_unifiac-lite.dts
@ -5,5 +5,5 @@

 / {
 	compatible = "ubnt,unifiac-lite", "qca,qca9563";
-	model = "Ubiquiti UniFi-AC-LITE";
+	model = "Ubiquiti UniFi AC Lite";
 };
--- a/target/linux/ath79/dts/qca9563_ubnt_unifiac-lr.dts
+++ b/target/linux/ath79/dts/qca9563_ubnt_unifiac-lr.dts
@ -5,5 +5,5 @@

 / {
 	compatible = "ubnt,unifiac-lr", "qca,qca9563";
-	model = "Ubiquiti UniFi-AC-LR";
+	model = "Ubiquiti UniFi AC LR";
 };
--- a/target/linux/ath79/dts/qca9563_ubnt_unifiac-mesh-pro.dts
+++ b/target/linux/ath79/dts/qca9563_ubnt_unifiac-mesh-pro.dts
@ -5,5 +5,5 @@

 / {
 	compatible = "ubnt,unifiac-mesh-pro", "qca,qca9563";
-	model = "Ubiquiti UniFi-AC-MESH PRO";
+	model = "Ubiquiti UniFi AC Mesh Pro";
 };
--- a/target/linux/ath79/dts/qca9563_ubnt_unifiac-mesh.dts
+++ b/target/linux/ath79/dts/qca9563_ubnt_unifiac-mesh.dts
@ -5,5 +5,5 @@

 / {
 	compatible = "ubnt,unifiac-mesh", "qca,qca9563";
-	model = "Ubiquiti UniFi-AC-MESH";
+	model = "Ubiquiti UniFi AC Mesh";
 };
--- a/target/linux/ath79/dts/qca9563_ubnt_unifiac-pro.dts
+++ b/target/linux/ath79/dts/qca9563_ubnt_unifiac-pro.dts
@ -5,7 +5,7 @@

 / {
 	compatible = "ubnt,unifiac-pro", "qca,qca9563";
-	model = "Ubiquiti UniFi-AC-PRO";
+	model = "Ubiquiti UniFi AC Pro";
 };

 &usb_phy0 {
--- a/target/linux/ath79/generic/base-files/etc/board.d/01_leds
+++ b/target/linux/ath79/generic/base-files/etc/board.d/01_leds
@ -315,6 +315,7 @@ ubnt,nanostation-loco-m-xw|\
 ubnt,nanostation-m|\
 ubnt,nanostation-m-xw|\
 ubnt,picostation-m|\
+ubnt,powerbridge-m|\
 ubnt,rocket-m)
 	ucidef_set_rssimon "wlan0" "200000" "1"
 	ucidef_set_led_rssi "rssilow" "RSSILOW" "ubnt:red:link1" "wlan0" "1" "100"
--- a/target/linux/ath79/generic/base-files/etc/board.d/02_network
+++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network
@ -63,6 +63,7 @@ ath79_setup_interfaces()
 	ubnt,picostation-m|\
 	ubnt,powerbeam-5ac-500|\
 	ubnt,powerbeam-5ac-gen2|\
+	ubnt,powerbridge-m|\
 	ubnt,rocket-m|\
 	ubnt,unifiac-lite|\
 	ubnt,unifiac-lr|\
@ -513,6 +514,7 @@ ath79_setup_macs()
 	ubnt,nanostation-loco-m|\
 	ubnt,nanostation-m|\
 	ubnt,picostation-m|\
+	ubnt,powerbridge-m|\
 	ubnt,rocket-m|\
 	ubnt,unifi)
 		label_mac=$(cat /sys/class/ieee80211/phy0/macaddress)
--- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
+++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
@ -111,6 +111,7 @@ case "$FIRMWARE" in
 	ubnt,nanostation-loco-m|\
 	ubnt,nanostation-m|\
 	ubnt,picostation-m|\
+	ubnt,powerbridge-m|\
 	ubnt,rocket-m)
 		caldata_extract "art" 0x1000 0x1000
 		;;
--- a/target/linux/ath79/image/generic-ubnt.mk
+++ b/target/linux/ath79/image/generic-ubnt.mk
@ -125,7 +125,7 @@ TARGET_DEVICES += ubnt_airrouter
 define Device/ubnt_bullet-m-ar7240
  $(Device/ubnt-xm)
  SOC := ar7240
-  DEVICE_MODEL := Bullet-M
+  DEVICE_MODEL := Bullet M
  DEVICE_VARIANT := XM (AR7240)
  DEVICE_PACKAGES += rssileds
  SUPPORTED_DEVICES += bullet-m
@ -135,7 +135,7 @@ TARGET_DEVICES += ubnt_bullet-m-ar7240
 define Device/ubnt_bullet-m-ar7241
  $(Device/ubnt-xm)
  SOC := ar7241
-  DEVICE_MODEL := Bullet-M
+  DEVICE_MODEL := Bullet M
  DEVICE_VARIANT := XM (AR7241)
  DEVICE_PACKAGES += rssileds
  SUPPORTED_DEVICES += bullet-m ubnt,bullet-m
@ -144,7 +144,7 @@ TARGET_DEVICES += ubnt_bullet-m-ar7241

 define Device/ubnt_bullet-m-xw
  $(Device/ubnt-xw)
-  DEVICE_MODEL := Bullet-M
+  DEVICE_MODEL := Bullet M
  DEVICE_PACKAGES += rssileds
  SUPPORTED_DEVICES += bullet-m-xw
 endef
@ -165,8 +165,7 @@ TARGET_DEVICES += ubnt_edgeswitch-8xp

 define Device/ubnt_lap-120
  $(Device/ubnt-wa)
-  DEVICE_MODEL := LiteAP ac
-  DEVICE_VARIANT := LAP-120
+  DEVICE_MODEL := LiteAP ac (LAP-120)
  DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct
 endef
 TARGET_DEVICES += ubnt_lap-120
@ -269,10 +268,19 @@ define Device/ubnt_powerbeam-5ac-gen2
 endef
 TARGET_DEVICES += ubnt_powerbeam-5ac-gen2

+define Device/ubnt_powerbridge-m
+  $(Device/ubnt-xm)
+  SOC := ar7241
+  DEVICE_MODEL := PowerBridge M
+  DEVICE_PACKAGES += rssileds
+  SUPPORTED_DEVICES += bullet-m
+endef
+TARGET_DEVICES += ubnt_powerbridge-m
+
 define Device/ubnt_rocket-m
  $(Device/ubnt-xm)
  SOC := ar7241
-  DEVICE_MODEL := Rocket-M
+  DEVICE_MODEL := Rocket M
  DEVICE_PACKAGES += rssileds
  SUPPORTED_DEVICES += rocket-m
 endef
@ -328,35 +336,35 @@ endef

 define Device/ubnt_unifiac-lite
  $(Device/ubnt_unifiac)
-  DEVICE_MODEL := UniFi AC-Lite
+  DEVICE_MODEL := UniFi AC Lite
  SUPPORTED_DEVICES += unifiac-lite
 endef
 TARGET_DEVICES += ubnt_unifiac-lite

 define Device/ubnt_unifiac-lr
  $(Device/ubnt_unifiac)
-  DEVICE_MODEL := UniFi AC-LR
+  DEVICE_MODEL := UniFi AC LR
  SUPPORTED_DEVICES += unifiac-lite ubnt,unifiac-lite
 endef
 TARGET_DEVICES += ubnt_unifiac-lr

 define Device/ubnt_unifiac-mesh
  $(Device/ubnt_unifiac)
-  DEVICE_MODEL := UniFi AC-Mesh
+  DEVICE_MODEL := UniFi AC Mesh
  SUPPORTED_DEVICES += unifiac-lite
 endef
 TARGET_DEVICES += ubnt_unifiac-mesh

 define Device/ubnt_unifiac-mesh-pro
  $(Device/ubnt_unifiac)
-  DEVICE_MODEL := UniFi AC-Mesh Pro
+  DEVICE_MODEL := UniFi AC Mesh Pro
  SUPPORTED_DEVICES += unifiac-pro
 endef
 TARGET_DEVICES += ubnt_unifiac-mesh-pro

 define Device/ubnt_unifiac-pro
  $(Device/ubnt_unifiac)
-  DEVICE_MODEL := UniFi AC-Pro
+  DEVICE_MODEL := UniFi AC Pro
  DEVICE_PACKAGES += kmod-usb2
  SUPPORTED_DEVICES += unifiac-pro
 endef
--- a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_uimage.c
+++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_uimage.c
@ -407,6 +407,43 @@ static struct mtd_part_parser uimage_fonfxc_parser = {
 	.parse_fn = mtdsplit_uimage_parse_fonfxc,
 };

+/**************************************************
+ * SGE (T&W) Shenzhen Gongjin Electronics
+ **************************************************/
+
+#define SGE_PAD_LEN		96
+
+static ssize_t uimage_find_sge(u_char *buf, size_t len, int *extralen)
+{
+	if (uimage_verify_default(buf, len, extralen) < 0)
+		return -EINVAL;
+
+	*extralen = SGE_PAD_LEN;
+
+	return 0;
+}
+
+static int
+mtdsplit_uimage_parse_sge(struct mtd_info *master,
+			      const struct mtd_partition **pparts,
+			      struct mtd_part_parser_data *data)
+{
+	return __mtdsplit_parse_uimage(master, pparts, data,
+				       uimage_find_sge);
+}
+
+static const struct of_device_id mtdsplit_uimage_sge_of_match_table[] = {
+	{ .compatible = "sge,uimage" },
+	{},
+};
+
+static struct mtd_part_parser uimage_sge_parser = {
+	.owner = THIS_MODULE,
+	.name = "sge-fw",
+	.of_match_table = mtdsplit_uimage_sge_of_match_table,
+	.parse_fn = mtdsplit_uimage_parse_sge,
+};
+
 /**************************************************
 * OKLI (OpenWrt Kernel Loader Image)
 **************************************************/
@ -470,6 +507,7 @@ static int __init mtdsplit_uimage_init(void)
 	register_mtd_parser(&uimage_netgear_parser);
 	register_mtd_parser(&uimage_edimax_parser);
 	register_mtd_parser(&uimage_fonfxc_parser);
+	register_mtd_parser(&uimage_sge_parser);
 	register_mtd_parser(&uimage_okli_parser);

 	return 0;
--- a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
+++ b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
@ -968,7 +968,6 @@ static int edma_axi_probe(struct platform_device *pdev)
 		edma_netdev[i]->netdev_ops = &edma_axi_netdev_ops;
 		edma_netdev[i]->max_mtu = 9000;
 		edma_netdev[i]->features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM
-				      | NETIF_F_HW_VLAN_CTAG_TX
 				      | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_SG |
 				      NETIF_F_TSO | NETIF_F_GRO;
 		edma_netdev[i]->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
@ -980,10 +979,10 @@ static int edma_axi_probe(struct platform_device *pdev)
 					     NETIF_F_TSO | NETIF_F_GRO;

 #ifdef CONFIG_RFS_ACCEL
-		edma_netdev[i]->features |=  NETIF_F_RXHASH | NETIF_F_NTUPLE;
-		edma_netdev[i]->hw_features |=  NETIF_F_RXHASH | NETIF_F_NTUPLE;
-		edma_netdev[i]->vlan_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
-		edma_netdev[i]->wanted_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
+		edma_netdev[i]->features |=  NETIF_F_NTUPLE;
+		edma_netdev[i]->hw_features |=  NETIF_F_NTUPLE;
+		edma_netdev[i]->vlan_features |= NETIF_F_NTUPLE;
+		edma_netdev[i]->wanted_features |= NETIF_F_NTUPLE;
 #endif
 		edma_set_ethtool_ops(edma_netdev[i]);

--- a/target/linux/ipq40xx/patches-5.4/705-net-add-qualcomm-ar40xx-phy.patch
+++ b/target/linux/ipq40xx/patches-5.4/705-net-add-qualcomm-ar40xx-phy.patch
@ -1,5 +1,7 @@
--- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
+Index: linux-5.4.51/drivers/net/phy/Kconfig
+===================================================================
+--- linux-5.4.51.orig/drivers/net/phy/Kconfig
+++ linux-5.4.51/drivers/net/phy/Kconfig
@@ -587,6 +587,13 @@ config MDIO_IPQ40XX
 	  This driver supports the MDIO interface found in Qualcomm
 	  Atheros ipq40xx Soc chip.
@ -14,8 +16,10 @@
 endif # PHYLIB
 
 config MICREL_KS8995MA
--- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
+Index: linux-5.4.51/drivers/net/phy/Makefile
+===================================================================
+--- linux-5.4.51.orig/drivers/net/phy/Makefile
+++ linux-5.4.51/drivers/net/phy/Makefile
@@ -70,6 +70,7 @@ ifdef CONFIG_HWMON
 aquantia-objs			+= aquantia_hwmon.o
 endif
@ -24,9 +28,11 @@
 obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o
 obj-$(CONFIG_AT803X_PHY)	+= at803x.o
 obj-$(CONFIG_BCM63XX_PHY)	+= bcm63xx.o
+Index: linux-5.4.51/drivers/net/phy/ar40xx.c
+===================================================================
 --- /dev/null
-+++ b/drivers/net/phy/ar40xx.c
-@@ -0,0 +1,2123 @@
+++ linux-5.4.51/drivers/net/phy/ar40xx.c
+@@ -0,0 +1,2118 @@
 +/*
 + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
 + *
@ -1261,7 +1267,11 @@
 +	ar40xx_rmw(priv, AR40XX_REG_PORT_STATUS(port),
 +			AR40XX_PORT_AUTO_LINK_EN, 0);
 +
-+	ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0);
+	/* CPU port is setting headers to limit output ports */
+	if (port == 0)
+		ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0x8);
+	else
+		ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0);
 +
 +	ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), 0);
 +
@ -1304,6 +1314,10 @@
 +	t = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16) |
 +	      AR40XX_PORT0_FC_THRESH_OFF_DFLT;
 +	ar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t);
+
+	/* set service tag to 802.1q */
+	t = ETH_P_8021Q | AR40XX_ESS_SERVICE_TAG_STAG;
+	ar40xx_write(priv, AR40XX_ESS_SERVICE_TAG, t);
 +}
 +
 +static void
@ -1629,7 +1643,11 @@
 +	u32 pvid = priv->vlan_id[priv->pvid[port]];
 +
 +	if (priv->vlan) {
-+		egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;
+		if (priv->vlan_tagged & BIT(port))
+			egress = AR40XX_PORT_VLAN1_OUT_MODE_TAG;
+		else
+			egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;
+
 +		ingress = AR40XX_IN_SECURE;
 +	} else {
 +		egress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH;
@ -1640,8 +1658,17 @@
 +	t |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;
 +	ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), t);
 +
-+	t = AR40XX_PORT_VLAN1_PORT_VLAN_PROP;
-+	t |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S;
+	t = egress << AR40XX_PORT_VLAN1_OUT_MODE_S;
+
+	/* set CPU port to core port */
+	if (port == 0)
+		t |= AR40XX_PORT_VLAN1_CORE_PORT;
+
+	if (priv->vlan_tagged & BIT(port))
+		t |= AR40XX_PORT_VLAN1_PORT_VLAN_PROP;
+	else
+		t |= AR40XX_PORT_VLAN1_PORT_TLS_MODE;
+
 +	ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
 +
 +	t = members;
@ -2083,6 +2110,12 @@
 +	/* register switch */
 +	swdev = &priv->dev;
 +
+	if (priv->mii_bus == NULL) {
+		dev_err(&pdev->dev, "Probe failed - Missing PHYs!\n");
+		ret = -ENODEV;
+		goto err_missing_phy;
+	}
+
 +	swdev->alias = dev_name(&priv->mii_bus->dev);
 +
 +	swdev->cpu_port = AR40XX_PORT_CPU;
@ -2114,6 +2147,7 @@
 +	unregister_switch(&priv->dev);
 +err_unregister_phy:
 +	phy_driver_unregister(&ar40xx_phy_driver);
+err_missing_phy:
 +	platform_set_drvdata(pdev, NULL);
 +	return ret;
 +}
@ -2150,9 +2184,11 @@
 +
 +MODULE_DESCRIPTION("IPQ40XX ESS driver");
 +MODULE_LICENSE("Dual BSD/GPL");
+Index: linux-5.4.51/drivers/net/phy/ar40xx.h
+===================================================================
 --- /dev/null
-+++ b/drivers/net/phy/ar40xx.h
-@@ -0,0 +1,337 @@
+++ linux-5.4.51/drivers/net/phy/ar40xx.h
+@@ -0,0 +1,342 @@
 +/*
 + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
 + *
@ -2306,6 +2342,9 @@
 +#define   AR40XX_MIB_FUNC_NO_OP		0x0
 +#define   AR40XX_MIB_FUNC_FLUSH		0x1
 +
+#define AR40XX_ESS_SERVICE_TAG		0x48
+#define AR40XX_ESS_SERVICE_TAG_STAG	BIT(17)
+
 +#define AR40XX_REG_PORT_STATUS(_i)		(0x07c + (_i) * 4)
 +#define   AR40XX_PORT_SPEED			BITS(0, 2)
 +#define   AR40XX_PORT_STATUS_SPEED_S	0
@ -2334,6 +2373,8 @@
 +#define   AR40XX_PORT_VLAN0_DEF_CVID_S		16
 +
 +#define AR40XX_REG_PORT_VLAN1(_i)		(0x424 + (_i) * 0x8)
+#define   AR40XX_PORT_VLAN1_CORE_PORT		BIT(9)
+#define   AR40XX_PORT_VLAN1_PORT_TLS_MODE	BIT(7)
 +#define   AR40XX_PORT_VLAN1_PORT_VLAN_PROP	BIT(6)
 +#define   AR40XX_PORT_VLAN1_OUT_MODE		BITS(12, 2)
 +#define   AR40XX_PORT_VLAN1_OUT_MODE_S		12
--- a/target/linux/ipq40xx/patches-5.4/706-ar40xx-abort-probe-on-missig-phy.patch
+++ b/target/linux/ipq40xx/patches-5.4/706-ar40xx-abort-probe-on-missig-phy.patch
@ -1,23 +0,0 @@
--- a/drivers/net/phy/ar40xx.c
-+++ b/drivers/net/phy/ar40xx.c
-@@ -2021,6 +2021,12 @@ static int ar40xx_probe(struct platform_
- 	/* register switch */
- 	swdev = &priv->dev;
- 
-+	if (priv->mii_bus == NULL) {
-+		dev_err(&pdev->dev, "Probe failed - Missing PHYs!\n");
-+		ret = -ENODEV;
-+		goto err_missing_phy;
-+	}
-+
- 	swdev->alias = dev_name(&priv->mii_bus->dev);
- 
- 	swdev->cpu_port = AR40XX_PORT_CPU;
-@@ -2052,6 +2058,7 @@ err_unregister_switch:
- 	unregister_switch(&priv->dev);
- err_unregister_phy:
- 	phy_driver_unregister(&ar40xx_phy_driver);
-+err_missing_phy:
- 	platform_set_drvdata(pdev, NULL);
- 	return ret;
- }
--- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-db149.dts
+++ b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-db149.dts
@ -4,6 +4,10 @@
 	model = "Qualcomm IPQ8064/DB149";
 	compatible = "qcom,ipq8064-db149", "qcom,ipq8064";

+	aliases {
+		serial0 = &gsbi2_serial;
+	};
+
 	reserved-memory {
 		#address-cells = <1>;
 		#size-cells = <1>;
@ -14,11 +18,6 @@
 		};
 	};

-	alias {
-		serial0 = &uart2;
-		mdio-gpio0 = &mdio0;
-	};
-
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
@ -61,7 +60,8 @@
 		gsbi2: gsbi@12480000 {
 			qcom,mode = <GSBI_PROT_I2C_UART>;
 			status = "okay";
-			uart2: serial@12490000 {
+
+			gsbi2_serial: serial@12490000 {
 				status = "okay";
 			};
 		};
--- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi
@ -818,7 +818,7 @@

 			syscon-tcsr = <&tcsr>;

-			uart2: serial@12490000 {
+			gsbi2_serial: serial@12490000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x12490000 0x1000>,
 				      <0x12480000 0x1000>;
@ -893,7 +893,7 @@

 			syscon-tcsr = <&tcsr>;

-			uart5: serial@1a240000 {
+			gsbi5_serial: serial@1a240000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x1a240000 0x1000>,
 				      <0x1a200000 0x1000>;
--- a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-db149.dts
+++ b/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064-db149.dts
@ -4,6 +4,10 @@
 	model = "Qualcomm IPQ8064/DB149";
 	compatible = "qcom,ipq8064-db149", "qcom,ipq8064";

+	aliases {
+		serial0 = &gsbi2_serial;
+	};
+
 	reserved-memory {
 		#address-cells = <1>;
 		#size-cells = <1>;
@ -13,11 +17,6 @@
 			no-map;
 		};
 	};
-
-	alias {
-		serial0 = &uart2;
-		mdio-gpio0 = &mdio0;
-	};
 };

 &qcom_pinmux {
@ -33,7 +32,8 @@
 &gsbi2 {
 	qcom,mode = <GSBI_PROT_I2C_UART>;
 	status = "okay";
-	uart2: serial@12490000 {
+
+	gsbi2_serial: serial@12490000 {
 		status = "okay";
 	};
 };
@ -180,4 +180,4 @@
 	phy-mode = "sgmii";
 	qcom,id = <3>;
 	phy-handle = <&phy7>;
-};
+};
--- a/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064.dtsi
@ -876,7 +876,7 @@

 			syscon-tcsr = <&tcsr>;

-			uart2: serial@12490000 {
+			gsbi2_serial: serial@12490000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x12490000 0x1000>,
 					  <0x12480000 0x1000>;
@ -951,7 +951,7 @@

 			syscon-tcsr = <&tcsr>;

-			uart5: serial@1a240000 {
+			gsbi5_serial: serial@1a240000 {
 				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 				reg = <0x1a240000 0x1000>,
 					  <0x1a200000 0x1000>;
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts
@ -257,18 +257,16 @@
 	};
 };

-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
-	status = "okay";
+&pcie0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pcie0_pins>;
+        status = "okay";
+};

-	pcie@0,0 {
-		status = "okay";
-	};
-
-	pcie@1,0 {
-		status = "okay";
-	};
+&pcie1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pcie1_pins>;
+        status = "okay";
 };

 &pio {
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts
@ -165,19 +165,14 @@
        };
 };

-&pcie {
-	pinctrl-names = "default", "pcie1_pins";
-	pinctrl-0 = <&pcie0_pins>;
-	pinctrl-1 = <&pcie1_pins>;
-	status = "okay";
-
-	pcie@0,0 {
-		status = "okay";
-		mt7615@0,0 {
-			reg = <0x0000 0 0 0 0>;
-			mediatek,mtd-eeprom = <&factory 0x05000>;
-		};
-	};
+&pcie0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pcie0_pins>;
+        status = "okay";
+        mt7615@0,0 {
+		reg = <0x0000 0 0 0 0>;
+		mediatek,mtd-eeprom = <&factory 0x05000>;
+        };
 };

 &pio {
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts
@ -0,0 +1,646 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "mt7622.dtsi"
+#include "mt6380.dtsi"
+
+/ {
+	model = "MT7622_MT7531 RFB";
+	compatible = "mediatek,mt7622,ubi";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
+	};
+
+	cpus {
+		cpu@0 {
+			proc-supply = <&mt6380_vcpu_reg>;
+			sram-supply = <&mt6380_vm_reg>;
+		};
+
+		cpu@1 {
+			proc-supply = <&mt6380_vcpu_reg>;
+			sram-supply = <&mt6380_vm_reg>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		factory {
+			label = "factory";
+			linux,code = <BTN_0>;
+			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		wps {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gsw: gsw@0 {
+                compatible = "mediatek,mt753x";
+                mediatek,ethsys = <&ethsys>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+	leds {
+		compatible = "gpio-leds";
+
+		green {
+			label = "bpi-r64:pio:green";
+			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		red {
+			label = "bpi-r64:pio:red";
+			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	memory {
+		reg = <0 0x40000000 0 0x40000000>;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_5v: regulator-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&bch {
+	status = "okay";
+};
+
+&btif {
+	status = "okay";
+};
+
+&cir {
+	pinctrl-names = "default";
+	pinctrl-0 = <&irrx_pins>;
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-mode = "2500base-x";
+
+		fixed-link {
+			speed = <2500>;
+			full-duplex;
+			pause;
+		};
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "rgmii";
+
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+			pause;
+		};
+	};
+
+	mdio: mdio-bus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
+
+&gsw {
+        mediatek,mdio = <&mdio>;
+        mediatek,portmap = "llllw";
+        mediatek,mdio_master_pinmux = <0>;
+        reset-gpios = <&pio 54 0>;
+        interrupt-parent = <&pio>;
+        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+        status = "okay";
+
+        port5: port@5 {
+                compatible = "mediatek,mt753x-port";
+                reg = <5>;
+                phy-mode = "rgmii";
+                fixed-link {
+                        speed = <1000>;
+                        full-duplex;
+                };
+        };
+
+        port6: port@6 {
+                compatible = "mediatek,mt753x-port";
+                reg = <6>;
+                phy-mode = "sgmii";
+                fixed-link {
+                        speed = <2500>;
+                        full-duplex;
+                };
+        };
+};    
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&emmc_pins_default>;
+	pinctrl-1 = <&emmc_pins_uhs>;
+	status = "okay";
+	bus-width = <8>;
+	max-frequency = <50000000>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+	non-removable;
+};
+
+&mmc1 {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&sd0_pins_default>;
+	pinctrl-1 = <&sd0_pins_uhs>;
+	status = "okay";
+	bus-width = <4>;
+	max-frequency = <50000000>;
+	cap-sd-highspeed;
+	r_smpl = <1>;
+	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+};
+
+&nandc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&parallel_nand_pins>;
+	status = "disabled";
+};
+
+&nor_flash {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_nor_pins>;
+	status = "disabled";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+	};
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_pins>;
+	status = "okay";
+};
+
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+	status = "okay";
+};
+
+&pio {
+	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
+	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
+	 */
+	asm_sel {
+		gpio-hog;
+		gpios = <90 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+
+	/* eMMC is shared pin with parallel NAND */
+	emmc_pins_default: emmc-pins-default {
+		mux {
+			function = "emmc", "emmc_rst";
+			groups = "emmc";
+		};
+
+		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+		 */
+		conf-cmd-dat {
+			pins = "NDL0", "NDL1", "NDL2",
+			       "NDL3", "NDL4", "NDL5",
+			       "NDL6", "NDL7", "NRB";
+			input-enable;
+			bias-pull-up;
+		};
+
+		conf-clk {
+			pins = "NCLE";
+			bias-pull-down;
+		};
+	};
+
+	emmc_pins_uhs: emmc-pins-uhs {
+		mux {
+			function = "emmc";
+			groups = "emmc";
+		};
+
+		conf-cmd-dat {
+			pins = "NDL0", "NDL1", "NDL2",
+			       "NDL3", "NDL4", "NDL5",
+			       "NDL6", "NDL7", "NRB";
+			input-enable;
+			drive-strength = <4>;
+			bias-pull-up;
+		};
+
+		conf-clk {
+			pins = "NCLE";
+			drive-strength = <4>;
+			bias-pull-down;
+		};
+	};
+
+	eth_pins: eth-pins {
+		mux {
+			function = "eth";
+			groups = "mdc_mdio", "rgmii_via_gmac2";
+		};
+	};
+
+	i2c1_pins: i2c1-pins {
+		mux {
+			function = "i2c";
+			groups =  "i2c1_0";
+		};
+	};
+
+	i2c2_pins: i2c2-pins {
+		mux {
+			function = "i2c";
+			groups =  "i2c2_0";
+		};
+	};
+
+	i2s1_pins: i2s1-pins {
+		mux {
+			function = "i2s";
+			groups =  "i2s_out_mclk_bclk_ws",
+				  "i2s1_in_data",
+				  "i2s1_out_data";
+		};
+
+		conf {
+			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
+			       "I2S_WS", "I2S_MCLK";
+			drive-strength = <12>;
+			bias-pull-down;
+		};
+	};
+
+	irrx_pins: irrx-pins {
+		mux {
+			function = "ir";
+			groups =  "ir_1_rx";
+		};
+	};
+
+	irtx_pins: irtx-pins {
+		mux {
+			function = "ir";
+			groups =  "ir_1_tx";
+		};
+	};
+
+	/* Parallel nand is shared pin with eMMC */
+	parallel_nand_pins: parallel-nand-pins {
+		mux {
+			function = "flash";
+			groups = "par_nand";
+		};
+	};
+
+	pcie0_pins: pcie0-pins {
+		mux {
+			function = "pcie";
+			groups = "pcie0_pad_perst",
+				 "pcie0_1_waken",
+				 "pcie0_1_clkreq";
+		};
+	};
+
+	pcie1_pins: pcie1-pins {
+		mux {
+			function = "pcie";
+			groups = "pcie1_pad_perst",
+				 "pcie1_0_waken",
+				 "pcie1_0_clkreq";
+		};
+	};
+
+	pmic_bus_pins: pmic-bus-pins {
+		mux {
+			function = "pmic";
+			groups = "pmic_bus";
+		};
+	};
+
+	pwm7_pins: pwm1-2-pins {
+		mux {
+			function = "pwm";
+			groups = "pwm_ch7_2";
+		};
+	};
+
+	wled_pins: wled-pins {
+		mux {
+			function = "led";
+			groups = "wled";
+		};
+	};
+
+	sd0_pins_default: sd0-pins-default {
+		mux {
+			function = "sd";
+			groups = "sd_0";
+		};
+
+		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+		 *  DAT2, DAT3, CMD, CLK for SD respectively.
+		 */
+		conf-cmd-data {
+			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+			       "I2S2_IN","I2S4_OUT";
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+		conf-clk {
+			pins = "I2S3_OUT";
+			drive-strength = <12>;
+			bias-pull-down;
+		};
+		conf-cd {
+			pins = "TXD3";
+			bias-pull-up;
+		};
+	};
+
+	sd0_pins_uhs: sd0-pins-uhs {
+		mux {
+			function = "sd";
+			groups = "sd_0";
+		};
+
+		conf-cmd-data {
+			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+			       "I2S2_IN","I2S4_OUT";
+			input-enable;
+			bias-pull-up;
+		};
+
+		conf-clk {
+			pins = "I2S3_OUT";
+			bias-pull-down;
+		};
+	};
+
+	/* Serial NAND is shared pin with SPI-NOR */
+	serial_nand_pins: serial-nand-pins {
+		mux {
+			function = "flash";
+			groups = "snfi";
+		};
+	};
+
+	spic0_pins: spic0-pins {
+		mux {
+			function = "spi";
+			groups = "spic0_0";
+		};
+	};
+
+	spic1_pins: spic1-pins {
+		mux {
+			function = "spi";
+			groups = "spic1_0";
+		};
+	};
+
+	/* SPI-NOR is shared pin with serial NAND */
+	spi_nor_pins: spi-nor-pins {
+		mux {
+			function = "flash";
+			groups = "spi_nor";
+		};
+	};
+
+	/* serial NAND is shared pin with SPI-NOR */
+	serial_nand_pins: serial-nand-pins {
+		mux {
+			function = "flash";
+			groups = "snfi";
+		};
+	};
+
+	uart0_pins: uart0-pins {
+		mux {
+			function = "uart";
+			groups = "uart0_0_tx_rx" ;
+		};
+	};
+
+	uart2_pins: uart2-pins {
+		mux {
+			function = "uart";
+			groups = "uart2_1_tx_rx" ;
+		};
+	};
+
+	watchdog_pins: watchdog-pins {
+		mux {
+			function = "watchdog";
+			groups = "watchdog";
+		};
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm7_pins>;
+	status = "okay";
+};
+
+&pwrap {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pmic_bus_pins>;
+
+	status = "okay";
+};
+
+&sata {
+	status = "disable";
+};
+
+&sata_phy {
+	status = "disable";
+};
+
+&snfi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&serial_nand_pins>;
+	status = "okay";
+
+	spi_nand@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "Preloader";
+				reg = <0x00000 0x0080000>;
+				read-only;
+			};
+
+			partition@80000 {
+				label = "ATF";
+				reg = <0x80000 0x0040000>;
+			};
+
+			partition@c0000 {
+				label = "Bootloader";
+				reg = <0xc0000 0x0080000>;
+			};
+
+			partition@140000 {
+				label = "Config";
+				reg = <0x140000 0x0080000>;
+			};
+
+			factory: partition@1c0000 {
+				label = "Factory";
+				reg = <0x1c0000 0x0040000>;
+			};
+
+			partition@200000 {
+				label = "kernel";
+				reg = <0x200000 0x400000>;
+			};
+
+			partition@600000 {
+				label = "ubi";
+				reg = <0x600000 0x1C00000>;
+			};
+
+			partition@2200000 {
+				label = "User_data";
+				reg = <0x2200000 0x4000000>;
+			};
+		};
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spic0_pins>;
+	status = "okay";
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spic1_pins>;
+	status = "okay";
+};
+
+&ssusb {
+	vusb33-supply = <&reg_3p3v>;
+	vbus-supply = <&reg_5v>;
+	status = "okay";
+};
+
+&u3phy {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+	status = "okay";
+};
+
+&watchdog {
+	pinctrl-names = "default";
+	pinctrl-0 = <&watchdog_pins>;
+	status = "okay";
+};
+
+&wmac {
+	mediatek,mtd-eeprom = <&factory 0x0000>;
+	status = "okay";
+};
--- a/target/linux/mediatek/image/mt7622.mk
+++ b/target/linux/mediatek/image/mt7622.mk
@ -1,4 +1,4 @@
-KERNEL_LOADADDR := 0x41080000
+KERNEL_LOADADDR := 0x44080000

 define Device/bpi_bananapi-r64
  DEVICE_VENDOR := Bpi
@ -40,3 +40,21 @@ define Device/mediatek_mt7622-rfb1
  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb3 kmod-ata-ahci-mtk
 endef
 TARGET_DEVICES += mediatek_mt7622-rfb1
+
+define Device/mediatek_mt7622-ubi
+  DEVICE_VENDOR := MediaTek
+  DEVICE_MODEL := MTK7622 AP (UBI)
+  DEVICE_DTS := mt7622-rfb1-ubi
+  DEVICE_DTS_DIR := $(DTS_DIR)/mediatek
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  KERNEL_SIZE := 4194304
+  IMAGE_SIZE := 32768k
+  IMAGES += factory.bin
+  IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \
+                check-size $$$$(IMAGE_SIZE)
+  IMAGE/sysupgrade.bin := sysupgrade-tar
+  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb3 kmod-ata-ahci-mtk
+endef
+TARGET_DEVICES += mediatek_mt7622-ubi
--- a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
@ -7,6 +7,9 @@ platform_do_upgrade() {
 		#of eMMC and to the location of the kernel
 		get_image "$1" | dd of=/dev/mmcblk0 bs=2097152 seek=1 conv=fsync
 		;;
+	mediatek,mt7622,ubi)
+		nand_do_upgrade "$1"
+		;;
 	*)
 		default_do_upgrade "$1"
 		;;
--- a/target/linux/mediatek/mt7622/config-5.4
+++ b/target/linux/mediatek/mt7622/config-5.4
@ -197,9 +197,11 @@ CONFIG_CPU_FREQ_STAT=y
 CONFIG_CPU_RMAP=y
 CONFIG_CPU_THERMAL=y
 CONFIG_CRC16=y
+CONFIG_CRYPTO_ACOMP2=y
 CONFIG_CRYPTO_AEAD=y
 CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_DRBG=y
 CONFIG_CRYPTO_DRBG_HMAC=y
 CONFIG_CRYPTO_DRBG_MENU=y
@ -208,11 +210,13 @@ CONFIG_CRYPTO_ECC=y
 CONFIG_CRYPTO_ECDH=y
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HASH_INFO=y
 CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_JITTERENTROPY=y
 CONFIG_CRYPTO_KPP=y
 CONFIG_CRYPTO_KPP2=y
 CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LZO=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
 CONFIG_CRYPTO_NULL2=y
@ -277,6 +281,7 @@ CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GLOB=y
 CONFIG_GPIOLIB=y
+CONFIG_GRO_CELLS=y
 CONFIG_HANDLE_DOMAIN_IRQ=y
 CONFIG_HARDEN_BRANCH_PREDICTOR=y
 CONFIG_HARDIRQS_SW_RESEND=y
@ -340,6 +345,9 @@ CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
 CONFIG_HAVE_UID16=y
 CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
 CONFIG_HOLES_IN_ZONE=y
+# CONFIG_HW_NAT is not set
+CONFIG_HZ=250
+CONFIG_HZ_250=y
 CONFIG_ICPLUS_PHY=y
 CONFIG_IIO=y
 CONFIG_IKCONFIG=y
@ -378,10 +386,13 @@ CONFIG_JUMP_LABEL=y
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
 CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_MDIO_BUS=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MEDIATEK_MT6577_AUXADC=y
+# CONFIG_MEDIATEK_NETSYS_V2 is not set
 CONFIG_MEDIATEK_WATCHDOG=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEMFD_CREATE=y
@ -393,7 +404,7 @@ CONFIG_MMC_MTK=y
 # CONFIG_MMC_TIFM_SD is not set
 CONFIG_MODULES_TREE_LOOKUP=y
 CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MT753X_GSW is not set
+CONFIG_MT753X_GSW=y
 CONFIG_MTD_NAND_CORE=y
 CONFIG_MTD_NAND_ECC_SW_HAMMING=y
 CONFIG_MTD_NAND_MTK=y
@ -402,6 +413,12 @@ CONFIG_MTD_SPI_NAND=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_SPLIT_FIRMWARE=y
 CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
 # CONFIG_MTK_CMDQ is not set
 # CONFIG_MTK_CQDMA is not set
 CONFIG_MTK_EFUSE=y
@ -515,6 +532,7 @@ CONFIG_SERIAL_DEV_BUS=y
 CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
 CONFIG_SERIAL_MCTRL_GPIO=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SGL_ALLOC=y
 CONFIG_SG_POOL=y
 CONFIG_SMP=y
 CONFIG_SPARSEMEM=y
@ -553,6 +571,11 @@ CONFIG_TIMER_OF=y
 CONFIG_TIMER_PROBE=y
 CONFIG_TREE_RCU=y
 CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_ZSTD is not set
 # CONFIG_UCLAMP_TASK is not set
 # CONFIG_UNMAP_KERNEL_AT_EL0 is not set
 CONFIG_USB=y
@ -570,4 +593,6 @@ CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
 CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
 CONFIG_WATCHDOG_SYSFS=y
 CONFIG_XPS=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
 CONFIG_ZONE_DMA32=y
--- a/target/linux/mediatek/patches-5.4/0501-crypto-add-eip97-inside-secure-support.patch
+++ b/target/linux/mediatek/patches-5.4/0501-crypto-add-eip97-inside-secure-support.patch
@ -5,11 +5,11 @@
 		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
 	}
 +	/*
-+	 * Set maximum number of TX commands to 2^5 = 32 for EIP97 HW2.1
+	 * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3
 +	 */
 +	else {
 +		val = 0;
-+		val |= EIP97_MST_CTRL_TX_MAX_CMD(5);
+		val |= EIP97_MST_CTRL_TX_MAX_CMD(4);
 +		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
 +	}
 
--- a/target/linux/mediatek/patches-5.4/0991-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch
+++ b/target/linux/mediatek/patches-5.4/0991-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch
@ -0,0 +1,420 @@
+From patchwork Thu May 28 06:16:45 2020
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+From: <chuanjia.liu@mediatek.com>
+To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
+Subject: [PATCH v2 1/4] dt-bindings: PCI: Mediatek: Update PCIe binding
+Date: Thu, 28 May 2020 14:16:45 +0800
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+
+From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
+
+There are two independent PCIe controllers in MT2712/MT7622 platform,
+and each of them should contain an independent MSI domain.
+
+In current architecture, MSI domain will be inherited from the root
+bridge, and all of the devices will share the same MSI domain.
+Hence that, the PCIe devices will not work properly if the irq number
+which required is more than 32.
+
+Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
+comply with the hardware design.
+
+Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
+---
+ .../bindings/pci/mediatek-pcie-cfg.yaml       |  38 +++++
+ .../devicetree/bindings/pci/mediatek-pcie.txt | 144 +++++++++++-------
+ 2 files changed, 129 insertions(+), 53 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
+
+diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
+new file mode 100644
+index 000000000000..4d2835ab4858
+--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
+@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek PCIECFG controller
+
+maintainers:
+  - Chuanjia Liu <chuanjia.liu@mediatek.com>
+  - Jianjun Wang <jianjun.wang@mediatek.com>
+
+description: |
+  The MediaTek PCIECFG controller controls some feature about
+  LTSSM, ASPM and so on.
+
+properties:
+  compatible:
+      items:
+        - enum:
+            - mediatek,mt7622-pciecfg
+            - mediatek,mt7629-pciecfg
+        - const: syscon
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    pciecfg: pciecfg@1a140000 {
+        compatible = "mediatek,mt7622-pciecfg", "syscon";
+        reg = <0 0x1a140000 0 0x1000>;
+    };
+...
+diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+index 7468d666763a..ddae110d4379 100644
+--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+@@ -8,7 +8,7 @@ Required properties:
+ 	"mediatek,mt7623-pcie"
+ 	"mediatek,mt7629-pcie"
+ - device_type: Must be "pci"
+-- reg: Base addresses and lengths of the PCIe subsys and root ports.
+- reg: Base addresses and lengths of the root ports.
+ - reg-names: Names of the above areas to use during resource lookup.
+ - #address-cells: Address representation for root ports (must be 3)
+ - #size-cells: Size representation for root ports (must be 2)
+@@ -19,10 +19,10 @@ Required properties:
+    - sys_ckN :transaction layer and data link layer clock
+   Required entries for MT2701/MT7623:
+    - free_ck :for reference clock of PCIe subsys
+-  Required entries for MT2712/MT7622:
+  Required entries for MT2712/MT7622/MT7629:
+    - ahb_ckN :AHB slave interface operating clock for CSR access and RC
+ 	      initiated MMIO access
+-  Required entries for MT7622:
+  Required entries for MT7622/MT7629:
+    - axi_ckN :application layer MMIO channel operating clock
+    - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
+ 	      pcie_mac_ck/pcie_pipe_ck is turned off
+@@ -47,10 +47,13 @@ Required properties for MT7623/MT2701:
+ - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
+   number of root ports.
+ 
+-Required properties for MT2712/MT7622:
+Required properties for MT2712/MT7622/MT7629:
+ -interrupts: A list of interrupt outputs of the controller, must have one
+ 	     entry for each PCIe port
+ 
+Required properties for MT7622/MT7629:
+- mediatek,pcie-subsys: Should be a phandle of the pciecfg node.
+
+ In addition, the device tree node must have sub-nodes describing each
+ PCIe port interface, having the following mandatory properties:
+ 
+@@ -143,56 +146,73 @@ Examples for MT7623:
+ 
+ Examples for MT2712:
+ 
+-	pcie: pcie@11700000 {
+	pcie1: pcie@112ff000 {
+ 		compatible = "mediatek,mt2712-pcie";
+ 		device_type = "pci";
+-		reg = <0 0x11700000 0 0x1000>,
+-		      <0 0x112ff000 0 0x1000>;
+-		reg-names = "port0", "port1";
+		reg = <0 0x112ff000 0 0x1000>;
+		reg-names = "port1";
+ 		#address-cells = <3>;
+ 		#size-cells = <2>;
+-		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+-			 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+-			 <&pericfg CLK_PERI_PCIE0>,
+		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pcie_irq";
+		clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+ 			 <&pericfg CLK_PERI_PCIE1>;
+-		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+-		phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
+-		phy-names = "pcie-phy0", "pcie-phy1";
+		clock-names = "sys_ck1", "ahb_ck1";
+		phys = <&u3port1 PHY_TYPE_PCIE>;
+		phy-names = "pcie-phy1";
+ 		bus-range = <0x00 0xff>;
+-		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
+		ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;
+		status = "disabled";
+ 
+-		pcie0: pcie@0,0 {
+-			reg = <0x0000 0 0 0 0>;
+		slot1: pcie@1,0 {
+			reg = <0x0800 0 0 0 0>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			#interrupt-cells = <1>;
+ 			ranges;
+ 			interrupt-map-mask = <0 0 0 7>;
+-			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+-					<0 0 0 2 &pcie_intc0 1>,
+-					<0 0 0 3 &pcie_intc0 2>,
+-					<0 0 0 4 &pcie_intc0 3>;
+-			pcie_intc0: interrupt-controller {
+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+					<0 0 0 2 &pcie_intc1 1>,
+					<0 0 0 3 &pcie_intc1 2>,
+					<0 0 0 4 &pcie_intc1 3>;
+			pcie_intc1: interrupt-controller {
+ 				interrupt-controller;
+ 				#address-cells = <0>;
+ 				#interrupt-cells = <1>;
+ 			};
+ 		};
+	};
+ 
+-		pcie1: pcie@1,0 {
+-			reg = <0x0800 0 0 0 0>;
+	pcie0: pcie@11700000 {
+		compatible = "mediatek,mt2712-pcie";
+		device_type = "pci";
+		reg = <0 0x11700000 0 0x1000>;
+		reg-names = "port0";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pcie_irq";
+		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+			 <&pericfg CLK_PERI_PCIE0>;
+		clock-names = "sys_ck0", "ahb_ck0";
+		phys = <&u3port0 PHY_TYPE_PCIE>;
+		phy-names = "pcie-phy0";
+		bus-range = <0x00 0xff>;
+		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
+		status = "disabled";
+
+		slot0: pcie@0,0 {
+			reg = <0x0000 0 0 0 0>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			#interrupt-cells = <1>;
+ 			ranges;
+ 			interrupt-map-mask = <0 0 0 7>;
+-			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+-					<0 0 0 2 &pcie_intc1 1>,
+-					<0 0 0 3 &pcie_intc1 2>,
+-					<0 0 0 4 &pcie_intc1 3>;
+-			pcie_intc1: interrupt-controller {
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+			pcie_intc0: interrupt-controller {
+ 				interrupt-controller;
+ 				#address-cells = <0>;
+ 				#interrupt-cells = <1>;
+@@ -202,39 +222,31 @@ Examples for MT2712:
+ 
+ Examples for MT7622:
+ 
+-	pcie: pcie@1a140000 {
+	pcie0: pcie@1a143000 {
+ 		compatible = "mediatek,mt7622-pcie";
+ 		device_type = "pci";
+-		reg = <0 0x1a140000 0 0x1000>,
+-		      <0 0x1a143000 0 0x1000>,
+-		      <0 0x1a145000 0 0x1000>;
+-		reg-names = "subsys", "port0", "port1";
+		reg = <0 0x1a143000 0 0x1000>;
+		reg-names = "port0";
+		mediatek,pcie-cfg = <&pciecfg>;
+ 		#address-cells = <3>;
+ 		#size-cells = <2>;
+-		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+-			     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "pcie_irq";
+ 		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+-			 <&pciesys CLK_PCIE_P1_MAC_EN>,
+ 			 <&pciesys CLK_PCIE_P0_AHB_EN>,
+-			 <&pciesys CLK_PCIE_P1_AHB_EN>,
+ 			 <&pciesys CLK_PCIE_P0_AUX_EN>,
+-			 <&pciesys CLK_PCIE_P1_AUX_EN>,
+ 			 <&pciesys CLK_PCIE_P0_AXI_EN>,
+-			 <&pciesys CLK_PCIE_P1_AXI_EN>,
+ 			 <&pciesys CLK_PCIE_P0_OBFF_EN>,
+-			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
+-			 <&pciesys CLK_PCIE_P0_PIPE_EN>,
+-			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
+-		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+-			      "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+-			      "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
+-		phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
+-		phy-names = "pcie-phy0", "pcie-phy1";
+			 <&pciesys CLK_PCIE_P0_PIPE_EN>;
+		clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
+			      "axi_ck0", "obff_ck0", "pipe_ck0";
+
+ 		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ 		bus-range = <0x00 0xff>;
+-		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
+		ranges = <0x82000000 0 0x20000000  0 0x20000000  0 0x8000000>;
+		status = "disabled";
+ 
+-		pcie0: pcie@0,0 {
+		slot0: pcie@0,0 {
+ 			reg = <0x0000 0 0 0 0>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+@@ -251,8 +263,34 @@ Examples for MT7622:
+ 				#interrupt-cells = <1>;
+ 			};
+ 		};
+	};
+
+	pcie1: pcie@1a145000 {
+		compatible = "mediatek,mt7622-pcie";
+		device_type = "pci";
+		reg = <0 0x1a145000 0 0x1000>;
+		reg-names = "port1";
+		mediatek,pcie-cfg = <&pciecfg>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "pcie_irq";
+		clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
+			 /* designer has connect RC1 with p0_ahb clock */
+			 <&pciesys CLK_PCIE_P0_AHB_EN>,
+			 <&pciesys CLK_PCIE_P1_AUX_EN>,
+			 <&pciesys CLK_PCIE_P1_AXI_EN>,
+			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
+			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
+		clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
+			      "axi_ck1", "obff_ck1", "pipe_ck1";
+
+		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+		bus-range = <0x00 0xff>;
+		ranges = <0x82000000 0 0x28000000  0 0x28000000  0 0x8000000>;
+		status = "disabled";
+ 
+-		pcie1: pcie@1,0 {
+		slot1: pcie@1,0 {
+ 			reg = <0x0800 0 0 0 0>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
--- a/target/linux/mediatek/patches-5.4/0992-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch
+++ b/target/linux/mediatek/patches-5.4/0992-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch
@ -0,0 +1,219 @@
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+From: <chuanjia.liu@mediatek.com>
+To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
+Subject: [PATCH v2 2/4] PCI: mediatek: Use regmap to get shared pcie-cfg base
+Date: Thu, 28 May 2020 14:16:46 +0800
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+From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
+
+Use regmap to get shared pcie-cfg base and change
+the method to get pcie irq.
+
+Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
+---
+ drivers/pci/controller/pcie-mediatek.c | 25 ++++++++++++++++++-------
+ 1 file changed, 18 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
+index cb982891b22b..2268d6073eb6 100644
+--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
+@@ -14,6 +14,7 @@
+ #include <linux/irqchip/chained_irq.h>
+ #include <linux/irqdomain.h>
+ #include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+ #include <linux/msi.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
+@@ -23,6 +24,7 @@
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+ #include <linux/reset.h>
+ 
+ #include "../pci.h"
+@@ -205,6 +207,7 @@ struct mtk_pcie_port {
+  * struct mtk_pcie - PCIe host information
+  * @dev: pointer to PCIe device
+  * @base: IO mapped register base
+ * @cfg: IO mapped register map for PCIe config
+  * @free_ck: free-run reference clock
+  * @mem: non-prefetchable memory resource
+  * @ports: pointer to PCIe port information
+@@ -214,6 +217,7 @@ struct mtk_pcie_port {
+ struct mtk_pcie {
+ 	struct device *dev;
+ 	void __iomem *base;
+	struct regmap *cfg;
+ 	struct clk *free_ck;
+ 
+ 	struct list_head ports;
+@@ -650,7 +654,7 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
+ 		return err;
+ 	}
+ 
+-	port->irq = platform_get_irq(pdev, port->slot);
+	port->irq = platform_get_irq_byname(pdev, "pcie_irq");
+ 	irq_set_chained_handler_and_data(port->irq,
+ 					 mtk_pcie_intr_handler, port);
+ 
+@@ -673,12 +677,11 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
+ 	if (!mem)
+ 		return -EINVAL;
+ 
+-	/* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
+-	if (pcie->base) {
+-		val = readl(pcie->base + PCIE_SYS_CFG_V2);
+-		val |= PCIE_CSR_LTSSM_EN(port->slot) |
+-		       PCIE_CSR_ASPM_L1_EN(port->slot);
+-		writel(val, pcie->base + PCIE_SYS_CFG_V2);
+	/* MT7622/MT7629 platforms need to enable LTSSM and ASPM. */
+	if (pcie->cfg) {
+		val = PCIE_CSR_LTSSM_EN(port->slot) |
+		      PCIE_CSR_ASPM_L1_EN(port->slot);
+		regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);
+ 	}
+ 
+ 	/* Assert all reset signals */
+@@ -984,6 +987,7 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
+ 	struct device *dev = pcie->dev;
+ 	struct platform_device *pdev = to_platform_device(dev);
+ 	struct resource *regs;
+	struct device_node *cfg_node;
+ 	int err;
+ 
+ 	/* get shared registers, which are optional */
+@@ -996,6 +1000,13 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
+ 		}
+ 	}
+ 
+	cfg_node = of_parse_phandle(dev->of_node, "mediatek,pcie-cfg", 0);
+	if (cfg_node) {
+		pcie->cfg = syscon_node_to_regmap(cfg_node);
+		if (IS_ERR(pcie->cfg))
+			return PTR_ERR(pcie->cfg);
+	}
+
+ 	pcie->free_ck = devm_clk_get(dev, "free_ck");
+ 	if (IS_ERR(pcie->free_ck)) {
+ 		if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
--- a/target/linux/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
+++ b/target/linux/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
@ -0,0 +1,423 @@
+From patchwork Thu May 28 06:16:47 2020
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+Subject: [PATCH v2 3/4] arm64: dts: mediatek: Split PCIe node for
+ MT2712/MT7622
+Date: Thu, 28 May 2020 14:16:47 +0800
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+ srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
+ linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
+ jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org,
+ yong.wu@mediatek.com, bhelgaas@google.com,
+ linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk
+Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
+Errors-To: 
+ linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
+
+From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
+
+There are two independent PCIe controllers in MT2712/MT7622 platform,
+and each of them should contain an independent MSI domain.
+
+In current architecture, MSI domain will be inherited from the root
+bridge, and all of the devices will share the same MSI domain.
+Hence that, the PCIe devices will not work properly if the irq number
+which required is more than 32.
+
+Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
+comply with the hardware design.
+
+Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
+---
+ arch/arm64/boot/dts/mediatek/mt2712e.dtsi     | 75 +++++++++++--------
+ .../dts/mediatek/mt7622-bananapi-bpi-r64.dts  | 16 ++--
+ arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts  |  6 +-
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi      | 68 +++++++++++------
+ 4 files changed, 96 insertions(+), 69 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+index 2cd8b33886e5..ab27ff4a869e 100644
+--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+@@ -797,60 +797,73 @@
+ 		};
+ 	};
+ 
+-	pcie: pcie@11700000 {
+	pcie1: pcie@112ff000 {
+ 		compatible = "mediatek,mt2712-pcie";
+ 		device_type = "pci";
+-		reg = <0 0x11700000 0 0x1000>,
+-		      <0 0x112ff000 0 0x1000>;
+-		reg-names = "port0", "port1";
+		reg = <0 0x112ff000 0 0x1000>;
+		reg-names = "port1";
+ 		#address-cells = <3>;
+ 		#size-cells = <2>;
+-		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+-			 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+-			 <&pericfg CLK_PERI_PCIE0>,
+		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pcie_irq";
+		clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+ 			 <&pericfg CLK_PERI_PCIE1>;
+-		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+-		phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
+-		phy-names = "pcie-phy0", "pcie-phy1";
+		clock-names = "sys_ck1", "ahb_ck1";
+		phys = <&u3port1 PHY_TYPE_PCIE>;
+		phy-names = "pcie-phy1";
+ 		bus-range = <0x00 0xff>;
+-		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
+		ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;
+		status = "disabled";
+ 
+-		pcie0: pcie@0,0 {
+-			device_type = "pci";
+-			status = "disabled";
+-			reg = <0x0000 0 0 0 0>;
+		slot1: pcie@1,0 {
+			reg = <0x0800 0 0 0 0>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			#interrupt-cells = <1>;
+ 			ranges;
+ 			interrupt-map-mask = <0 0 0 7>;
+-			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+-					<0 0 0 2 &pcie_intc0 1>,
+-					<0 0 0 3 &pcie_intc0 2>,
+-					<0 0 0 4 &pcie_intc0 3>;
+-			pcie_intc0: interrupt-controller {
+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+					<0 0 0 2 &pcie_intc1 1>,
+					<0 0 0 3 &pcie_intc1 2>,
+					<0 0 0 4 &pcie_intc1 3>;
+			pcie_intc1: interrupt-controller {
+ 				interrupt-controller;
+ 				#address-cells = <0>;
+ 				#interrupt-cells = <1>;
+ 			};
+ 		};
+	};
+ 
+-		pcie1: pcie@1,0 {
+-			device_type = "pci";
+-			status = "disabled";
+-			reg = <0x0800 0 0 0 0>;
+	pcie0: pcie@11700000 {
+		compatible = "mediatek,mt2712-pcie";
+		device_type = "pci";
+		reg = <0 0x11700000 0 0x1000>;
+		reg-names = "port0";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pcie_irq";
+		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+			 <&pericfg CLK_PERI_PCIE0>;
+		clock-names = "sys_ck0", "ahb_ck0";
+		phys = <&u3port0 PHY_TYPE_PCIE>;
+		phy-names = "pcie-phy0";
+		bus-range = <0x00 0xff>;
+		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+		status = "disabled";
+
+		slot0: pcie@0,0 {
+			reg = <0x0000 0 0 0 0>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			#interrupt-cells = <1>;
+ 			ranges;
+ 			interrupt-map-mask = <0 0 0 7>;
+-			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+-					<0 0 0 2 &pcie_intc1 1>,
+-					<0 0 0 3 &pcie_intc1 2>,
+-					<0 0 0 4 &pcie_intc1 3>;
+-			pcie_intc1: interrupt-controller {
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+			pcie_intc0: interrupt-controller {
+ 				interrupt-controller;
+ 				#address-cells = <0>;
+ 				#interrupt-cells = <1>;
+diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+index 83e10591e0e5..7574d88cc46a 100644
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -207,18 +207,16 @@
+ 	};
+ };
+ 
+-&pcie {
+&pcie0 {
+ 	pinctrl-names = "default";
+-	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
+	pinctrl-0 = <&pcie0_pins>;
+ 	status = "okay";
+};
+ 
+-	pcie@0,0 {
+-		status = "okay";
+-	};
+-
+-	pcie@1,0 {
+-		status = "okay";
+-	};
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+	status = "okay";
+ };
+ 
+ &pio {
+diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+index 339dc9f88f43..d5131c8b6a79 100644
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -766,45 +766,41 @@
+ 		#reset-cells = <1>;
+ 	};
+ 
+-	pcie: pcie@1a140000 {
+	pciecfg: pciecfg@1a140000 {
+		compatible = "mediatek,mt7622-pciecfg", "syscon";
+		reg = <0 0x1a140000 0 0x1000>;
+	};
+
+	pcie0: pcie@1a143000 {
+ 		compatible = "mediatek,mt7622-pcie";
+ 		device_type = "pci";
+-		reg = <0 0x1a140000 0 0x1000>,
+-		      <0 0x1a143000 0 0x1000>,
+-		      <0 0x1a145000 0 0x1000>;
+-		reg-names = "subsys", "port0", "port1";
+		reg = <0 0x1a143000 0 0x1000>;
+		reg-names = "port0";
+		mediatek,pcie-cfg = <&pciecfg>;
+ 		#address-cells = <3>;
+ 		#size-cells = <2>;
+-		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+-			     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "pcie_irq";
+ 		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+-			 <&pciesys CLK_PCIE_P1_MAC_EN>,
+-			 <&pciesys CLK_PCIE_P0_AHB_EN>,
+ 			 <&pciesys CLK_PCIE_P0_AHB_EN>,
+ 			 <&pciesys CLK_PCIE_P0_AUX_EN>,
+-			 <&pciesys CLK_PCIE_P1_AUX_EN>,
+ 			 <&pciesys CLK_PCIE_P0_AXI_EN>,
+-			 <&pciesys CLK_PCIE_P1_AXI_EN>,
+ 			 <&pciesys CLK_PCIE_P0_OBFF_EN>,
+-			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
+-			 <&pciesys CLK_PCIE_P0_PIPE_EN>,
+-			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
+-		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+-			      "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+-			      "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
+			 <&pciesys CLK_PCIE_P0_PIPE_EN>;
+		clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
+			      "axi_ck0", "obff_ck0", "pipe_ck0";
+
+ 		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ 		bus-range = <0x00 0xff>;
+-		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x8000000>;
+ 		status = "disabled";
+ 
+-		pcie0: pcie@0,0 {
+		slot0: pcie@0,0 {
+ 			reg = <0x0000 0 0 0 0>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			#interrupt-cells = <1>;
+ 			ranges;
+-			status = "disabled";
+-
+ 			interrupt-map-mask = <0 0 0 7>;
+ 			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ 					<0 0 0 2 &pcie_intc0 1>,
+@@ -816,15 +812,39 @@
+ 				#interrupt-cells = <1>;
+ 			};
+ 		};
+	};
+ 
+-		pcie1: pcie@1,0 {
+	pcie1: pcie@1a145000 {
+		compatible = "mediatek,mt7622-pcie";
+		device_type = "pci";
+		reg = <0 0x1a145000 0 0x1000>;
+		reg-names = "port1";
+		mediatek,pcie-cfg = <&pciecfg>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "pcie_irq";
+		clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
+			 /* designer has connect RC1 with p0_ahb clock */
+			 <&pciesys CLK_PCIE_P0_AHB_EN>,
+			 <&pciesys CLK_PCIE_P1_AUX_EN>,
+			 <&pciesys CLK_PCIE_P1_AXI_EN>,
+			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
+			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
+		clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
+			      "axi_ck1", "obff_ck1", "pipe_ck1";
+
+		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+		bus-range = <0x00 0xff>;
+		ranges = <0x82000000 0 0x28000000  0x0 0x28000000  0 0x8000000>;
+		status = "disabled";
+
+		slot1: pcie@1,0 {
+ 			reg = <0x0800 0 0 0 0>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			#interrupt-cells = <1>;
+ 			ranges;
+-			status = "disabled";
+-
+ 			interrupt-map-mask = <0 0 0 7>;
+ 			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ 					<0 0 0 2 &pcie_intc1 1>,
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts	2020-06-15 18:52:25.092948824 +0800
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts	2020-06-15 18:52:15.909094229 +0800
+@@ -244,18 +244,16 @@
+ 	};
+ };
+ 
+-&pcie {
+&pcie0 {
+ 	pinctrl-names = "default";
+-	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
+	pinctrl-0 = <&pcie0_pins>;
+ 	status = "okay";
+};
+ 
+-	pcie@0,0 {
+-		status = "okay";
+-	};
+-
+-	pcie@1,0 {
+-		status = "okay";
+-	};
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+	status = "okay";
+ };
+ 
+ &pio {
--- a/target/linux/mediatek/patches-5.4/0994-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch
+++ b/target/linux/mediatek/patches-5.4/0994-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch
@ -0,0 +1,207 @@
+From patchwork Thu May 28 06:16:48 2020
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+X-Patchwork-Id: 11574797
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+From: <chuanjia.liu@mediatek.com>
+To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
+Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node
+Date: Thu, 28 May 2020 14:16:48 +0800
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+Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
+ srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
+ linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
+ jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org,
+ yong.wu@mediatek.com, bhelgaas@google.com,
+ linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk
+Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
+Errors-To: 
+ linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
+
+From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
+
+Remove unused property and add pciecfg node.
+
+Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
+---
+ arch/arm/boot/dts/mt7629-rfb.dts |  3 ++-
+ arch/arm/boot/dts/mt7629.dtsi    | 23 +++++++++++++----------
+ 2 files changed, 15 insertions(+), 11 deletions(-)
+
+diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts
+index 9980c10c6e29..eb536cbebd9b 100644
+--- a/arch/arm/boot/dts/mt7629-rfb.dts
+++ b/arch/arm/boot/dts/mt7629-rfb.dts
+@@ -140,9 +140,10 @@
+ 	};
+ };
+ 
+-&pcie {
+&pcie1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pcie_pins>;
+	status = "okay";
+ };
+ 
+ &pciephy1 {
+diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
+index 5cbb3d244c75..94567307b842 100644
+--- a/arch/arm/boot/dts/mt7629.dtsi
+++ b/arch/arm/boot/dts/mt7629.dtsi
+@@ -360,16 +360,21 @@
+ 			#reset-cells = <1>;
+ 		};
+ 
+-		pcie: pcie@1a140000 {
+		pciecfg: pciecfg@1a140000 {
+			compatible = "mediatek,mt7629-pciecfg", "syscon";
+			reg = <0x1a140000 0x1000>;
+		};
+
+		pcie1: pcie@1a145000 {
+ 			compatible = "mediatek,mt7629-pcie";
+ 			device_type = "pci";
+-			reg = <0x1a140000 0x1000>,
+-			      <0x1a145000 0x1000>;
+-			reg-names = "subsys","port1";
+			reg = <0x1a145000 0x1000>;
+			reg-names = "port1";
+			mediatek,pcie-cfg = <&pciecfg>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+-			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
+-				     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+			interrupt-names = "pcie_irq";
+ 			clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
+ 				 <&pciesys CLK_PCIE_P0_AHB_EN>,
+ 				 <&pciesys CLK_PCIE_P1_AUX_EN>,
+@@ -390,21 +395,19 @@
+ 			power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ 			bus-range = <0x00 0xff>;
+ 			ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
+			status = "disabled";
+ 
+-			pcie1: pcie@1,0 {
+-				device_type = "pci";
+			slot1: pcie@1,0 {
+ 				reg = <0x0800 0 0 0 0>;
+ 				#address-cells = <3>;
+ 				#size-cells = <2>;
+ 				#interrupt-cells = <1>;
+ 				ranges;
+-				num-lanes = <1>;
+ 				interrupt-map-mask = <0 0 0 7>;
+ 				interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ 						<0 0 0 2 &pcie_intc1 1>,
+ 						<0 0 0 3 &pcie_intc1 2>,
+ 						<0 0 0 4 &pcie_intc1 3>;
+-
+ 				pcie_intc1: interrupt-controller {
+ 					interrupt-controller;
+ 					#address-cells = <0>;
--- a/target/linux/ramips/dts/mt7621_dlink_dir-878-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-878-a1.dts
@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "mt7621.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	compatible = "dlink,dir-878-a1", "mediatek,mt7621-soc";
+	model = "D-Link DIR-878 A1";
+
+	aliases {
+		led-boot = &led_power_orange;
+		led-failsafe = &led_power_green;
+		led-running = &led_power_green;
+		led-upgrade = &led_net_orange;
+		label-mac-device = &gmac0;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,57600";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_power_orange: power_orange {
+			label = "dir-878-a1:orange:power";
+			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_green: power_green {
+			label = "dir-878-a1:green:power";
+			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+		};
+
+		led_net_orange: net_orange {
+			label = "dir-878-a1:orange:net";
+			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+		};
+
+		net_green {
+			label = "dir-878-a1:green:net";
+			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+
+		wifi {
+			label = "wifi";
+			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RFKILL>;
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x30000>;
+				read-only;
+			};
+
+			partition@30000 {
+				label = "u-boot-env";
+				reg = <0x30000 0x10000>;
+				read-only;
+			};
+
+			factory: partition@40000 {
+				label = "factory";
+				reg = <0x40000 0x20000>;
+				read-only;
+			};
+
+			partition@60000 {
+				compatible = "sge,uimage";
+				label = "firmware";
+				reg = <0x60000 0xfa0000>;
+			};
+		};
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie0 {
+	wifi@0,0 {
+		compatible = "mediatek,mt76";
+		reg = <0x0000 0 0 0 0>;
+		mediatek,mtd-eeprom = <&factory 0x0000>;
+		ieee80211-freq-limit = <2400000 2500000>;
+
+		led {
+			led-active-low;
+		};
+	};
+};
+
+&pcie1 {
+	wifi@0,0 {
+		compatible = "mediatek,mt76";
+		reg = <0x0000 0 0 0 0>;
+		mediatek,mtd-eeprom = <&factory 0x8000>;
+		ieee80211-freq-limit = <5000000 6000000>;
+
+		led {
+			led-active-low;
+		};
+	};
+};
+
+&gmac0 {
+	mtd-mac-address = <&factory 0xe000>;
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			status = "okay";
+			label = "lan4";
+		};
+
+		port@1 {
+			status = "okay";
+			label = "lan3";
+		};
+
+		port@2 {
+			status = "okay";
+			label = "lan2";
+		};
+
+		port@3 {
+			status = "okay";
+			label = "lan1";
+		};
+
+		port@4 {
+			status = "okay";
+			label = "wan";
+			mtd-mac-address = <&factory 0xe006>;
+		};
+	};
+};
+
+&state_default {
+	gpio {
+		groups = "i2c", "uart3", "jtag", "wdt";
+		function = "gpio";
+	};
+};
--- a/target/linux/ramips/dts/mt7621_elecom_wrc-1750gs.dts
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-1750gs.dts
@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "mt7621_elecom_wrc-gs.dtsi"
+
+/ {
+	compatible = "elecom,wrc-1750gs", "mediatek,mt7621-soc";
+	model = "ELECOM WRC-1750GS";
+};
+
+&partitions {
+	partition@50000 {
+		compatible = "denx,uimage";
+		label = "firmware";
+		reg = <0x50000 0xb00000>;
+	};
+
+	partition@b50000 {
+		label = "tm_pattern";
+		reg = <0xb50000 0x380000>;
+		read-only;
+	};
+
+	partition@ed0000 {
+		label = "tm_key";
+		reg = <0xed0000 0x80000>;
+		read-only;
+	};
+
+	partition@f50000 {
+		label = "art_block";
+		reg = <0xf50000 0x30000>;
+		read-only;
+	};
+
+	partition@f80000 {
+		label = "user_data";
+		reg = <0xf80000 0x80000>;
+		read-only;
+	};
+};
--- a/target/linux/ramips/dts/mt7621_elecom_wrc-1750gsv.dts
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-1750gsv.dts
@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "mt7621_elecom_wrc-gs.dtsi"
+
+/ {
+	compatible = "elecom,wrc-1750gsv", "mediatek,mt7621-soc";
+	model = "ELECOM WRC-1750GSV";
+};
+
+&partitions {
+	partition@50000 {
+		compatible = "denx,uimage";
+		label = "firmware";
+		reg = <0x50000 0xb00000>;
+	};
+
+	partition@b50000 {
+		label = "tm_pattern";
+		reg = <0xb50000 0x380000>;
+		read-only;
+	};
+
+	partition@ed0000 {
+		label = "tm_key";
+		reg = <0xed0000 0x80000>;
+		read-only;
+	};
+
+	partition@f50000 {
+		label = "nvram";
+		reg = <0xf50000 0x30000>;
+		read-only;
+	};
+
+	partition@f80000 {
+		label = "user_data";
+		reg = <0xf80000 0x80000>;
+		read-only;
+	};
+};
--- a/target/linux/ramips/dts/mt7621_elecom_wrc-1900gst.dts
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-1900gst.dts
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;

-#include "mt7621_elecom_wrc-gst.dtsi"
+#include "mt7621_elecom_wrc-gs.dtsi"

 / {
 	compatible = "elecom,wrc-1900gst", "mediatek,mt7621-soc";
--- a/target/linux/ramips/dts/mt7621_elecom_wrc-2533gst.dts
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-2533gst.dts
@ -1,6 +1,6 @@
 /dts-v1/;

-#include "mt7621_elecom_wrc-gst.dtsi"
+#include "mt7621_elecom_wrc-gs.dtsi"

 / {
 	compatible = "elecom,wrc-2533gst", "mediatek,mt7621-soc";
--- a/target/linux/ramips/dts/mt7621_elecom_wrc-2533gst2.dts
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-2533gst2.dts
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;

-#include "mt7621_elecom_wrc-gst.dtsi"
+#include "mt7621_elecom_wrc-gs.dtsi"

 / {
 	compatible = "elecom,wrc-2533gst2", "mediatek,mt7621-soc";
--- a/target/linux/ramips/dts/mt7621_elecom_wrc-gst.dtsi
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-gst.dtsi
--- a/target/linux/ramips/dts/mt7621_linksys_ea7300-v1.dts
+++ b/target/linux/ramips/dts/mt7621_linksys_ea7300-v1.dts
@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "mt7621_linksys_ea7xxx.dtsi"
+
+/ {
+	compatible = "linksys,ea7300-v1", "mediatek,mt7621-soc";
+	model = "Linksys EA7300 v1";
+
+	aliases {
+		led-boot = &led_power;
+		led-failsafe = &led_power;
+		led-running = &led_power;
+		led-upgrade = &led_power;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wan_green {
+			label = "ea7300-v1:green:wan";
+			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+		};
+
+		lan1_green {
+			label = "ea7300-v1:green:lan1";
+			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+		};
+
+		lan2_green {
+			label = "ea7300-v1:green:lan2";
+			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+		};
+
+		lan3_green {
+			label = "ea7300-v1:green:lan3";
+			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+		};
+
+		lan4_green {
+			label = "ea7300-v1:green:lan4";
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power: power {
+			label = "ea7300-v1:white:power";
+			gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
+		};
+
+		wps {
+			label = "ea7300-v1:green:wps";
+			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
--- a/target/linux/ramips/dts/mt7621_linksys_ea7500-v2.dts
+++ b/target/linux/ramips/dts/mt7621_linksys_ea7500-v2.dts
@ -1,10 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;

-#include "mt7621.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
+#include "mt7621_linksys_ea7xxx.dtsi"

 / {
 	compatible = "linksys,ea7500-v2", "mediatek,mt7621-soc";
@ -17,10 +14,6 @@
 		led-upgrade = &led_power;
 	};

-	chosen {
-		bootargs = "console=ttyS0,115200";
-	};
-
 	leds {
 		compatible = "gpio-leds";

@ -59,149 +52,4 @@
 			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 		};
 	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "wps";
-			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&nand {
-	status = "okay";
-
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		partition@0 {
-			label = "boot";
-			reg = <0x0 0x80000>;
-			read-only;
-		};
-
-		partition@80000 {
-			label = "u_env";
-			reg = <0x80000 0x40000>;
-			read-only;
-		};
-
-		factory: partition@c0000 {
-			label = "factory";
-			reg = <0xc0000 0x40000>;
-			read-only;
-		};
-
-		partition@100000 {
-			label = "s_env";
-			reg = <0x100000 0x40000>;
-		};
-
-		partition@140000 {
-			label = "devinfo";
-			reg = <0x140000 0x40000>;
-			read-only;
-		};
-
-		partition@180000 {
-			label = "kernel";
-			reg = <0x180000 0x400000>;
-		};
-
-		partition@580000 {
-			label = "ubi";
-			reg = <0x580000 0x2400000>;
-		};
-
-		partition@2980000 {
-			label = "alt_kernel";
-			reg = <0x2980000 0x400000>;
-			read-only;
-		};
-
-		partition@2d80000 {
-			label = "alt_rootfs";
-			reg = <0x2d80000 0x2400000>;
-			read-only;
-		};
-
-		partition@5180000 {
-			label = "sysdiag";
-			reg = <0x5180000 0x100000>;
-			read-only;
-		};
-
-		partition@5280000 {
-			label = "syscfg";
-			reg = <0x5280000 0x2d00000>;
-			read-only;
-		};
-	};
-};
-
-&state_default {
-	gpio {
-		groups = "i2c", "uart2", "uart3", "jtag", "wdt";
-		function = "gpio";
-	};
-};
-
-&pcie {
-	status = "okay";
-};
-
-&pcie0 {
-	mt76@0,0 {
-		compatible = "mediatek,mt76";
-		reg = <0x0000 0 0 0 0>;
-		mediatek,mtd-eeprom = <&factory 0x0000>;
-	};
-};
-
-&pcie1 {
-	mt76@0,0 {
-		compatible = "mediatek,mt76";
-		reg = <0x0000 0 0 0 0>;
-		mediatek,mtd-eeprom = <&factory 0x8000>;
-	};
-};
-
-&switch0 {
-	ports {
-		port@0 {
-			status = "okay";
-			label = "wan";
-		};
-
-		port@1 {
-			status = "okay";
-			label = "lan1";
-		};
-
-		port@2 {
-			status = "okay";
-			label = "lan2";
-		};
-
-		port@3 {
-			status = "okay";
-			label = "lan3";
-		};
-
-		port@4 {
-			status = "okay";
-			label = "lan4";
-		};
-	};
 };
--- a/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi
+++ b/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi
@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+&nand {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "boot";
+			reg = <0x0 0x80000>;
+			read-only;
+		};
+
+		partition@80000 {
+			label = "u_env";
+			reg = <0x80000 0x40000>;
+			read-only;
+		};
+
+		factory: partition@c0000 {
+			label = "factory";
+			reg = <0xc0000 0x40000>;
+			read-only;
+		};
+
+		partition@100000 {
+			label = "s_env";
+			reg = <0x100000 0x40000>;
+		};
+
+		partition@140000 {
+			label = "devinfo";
+			reg = <0x140000 0x40000>;
+			read-only;
+		};
+
+		partition@180000 {
+			label = "kernel";
+			reg = <0x180000 0x400000>;
+		};
+
+		partition@580000 {
+			label = "ubi";
+			reg = <0x580000 0x2400000>;
+		};
+
+		partition@2980000 {
+			label = "alt_kernel";
+			reg = <0x2980000 0x400000>;
+			read-only;
+		};
+
+		partition@2d80000 {
+			label = "alt_rootfs";
+			reg = <0x2d80000 0x2400000>;
+			read-only;
+		};
+
+		partition@5180000 {
+			label = "sysdiag";
+			reg = <0x5180000 0x100000>;
+			read-only;
+		};
+
+		partition@5280000 {
+			label = "syscfg";
+			reg = <0x5280000 0x2d00000>;
+			read-only;
+		};
+	};
+};
+
+&state_default {
+	gpio {
+		groups = "i2c", "uart2", "uart3", "jtag", "wdt";
+		function = "gpio";
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie0 {
+	mt76@0,0 {
+		compatible = "mediatek,mt76";
+		reg = <0x0000 0 0 0 0>;
+		mediatek,mtd-eeprom = <&factory 0x0000>;
+	};
+};
+
+&pcie1 {
+	mt76@0,0 {
+		compatible = "mediatek,mt76";
+		reg = <0x0000 0 0 0 0>;
+		mediatek,mtd-eeprom = <&factory 0x8000>;
+	};
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			status = "okay";
+			label = "wan";
+		};
+
+		port@1 {
+			status = "okay";
+			label = "lan1";
+		};
+
+		port@2 {
+			status = "okay";
+			label = "lan2";
+		};
+
+		port@3 {
+			status = "okay";
+			label = "lan3";
+		};
+
+		port@4 {
+			status = "okay";
+			label = "lan4";
+		};
+	};
+};
--- a/target/linux/ramips/image/mt7621.mk
+++ b/target/linux/ramips/image/mt7621.mk
@ -7,7 +7,7 @@ include ./common-tp-link.mk
 DEFAULT_SOC := mt7621

 KERNEL_DTB += -d21
-DEVICE_VARS += UIMAGE_MAGIC
+DEVICE_VARS += UIMAGE_MAGIC ELECOM_HWNAME LINKSYS_HWNAME

 # The OEM webinterface expects an kernel with initramfs which has the uImage
 # header field ih_name.
@ -23,7 +23,7 @@ define Build/custom-initramfs-uimage
 	mv $@.new $@
 endef

-define Build/elecom-gst-factory
+define Build/elecom-wrc-gs-factory
 	$(eval product=$(word 1,$(1)))
 	$(eval version=$(word 2,$(1)))
 	( $(STAGING_DIR_HOST)/bin/mkhash md5 $@ | tr -d '\n' ) >> $@
@ -236,6 +236,21 @@ define Device/dlink_dir-860l-b1
 endef
 TARGET_DEVICES += dlink_dir-860l-b1

+define Device/dlink_dir-878-a1
+  IMAGE_SIZE := 16000k
+  DEVICE_VENDOR := D-Link
+  DEVICE_MODEL := DIR-878
+  DEVICE_VARIANT := A1
+  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware wpad-basic
+  KERNEL_INITRAMFS := $$(KERNEL) | uimage-padhdr 96
+  IMAGES += factory.bin
+  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | uimage-padhdr 96 |\
+	pad-rootfs | append-metadata | check-size
+  IMAGE/factory.bin := append-kernel | append-rootfs | uimage-padhdr 96 |\
+	check-size
+endef
+TARGET_DEVICES += dlink_dir-878-a1
+
 define Device/d-team_newifi-d2
  $(Device/uimage-lzma-loader)
  IMAGE_SIZE := 32448k
@ -311,39 +326,52 @@ define Device/elecom_wrc-1167ghbk2-s
 endef
 TARGET_DEVICES += elecom_wrc-1167ghbk2-s

-define Device/elecom_wrc-1900gst
+define Device/elecom_wrc-gs
  $(Device/uimage-lzma-loader)
-  IMAGE_SIZE := 11264k
  DEVICE_VENDOR := ELECOM
-  DEVICE_MODEL := WRC-1900GST
  IMAGES += factory.bin
  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \
-	elecom-gst-factory WRC-1900GST 0.00
+	elecom-wrc-gs-factory $$$$(ELECOM_HWNAME) 0.00
  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware wpad-basic
 endef
+
+define Device/elecom_wrc-1750gs
+  $(Device/elecom_wrc-gs)
+  IMAGE_SIZE := 11264k
+  DEVICE_MODEL := WRC-1750GS
+  ELECOM_HWNAME := WRC-1750GS
+endef
+TARGET_DEVICES += elecom_wrc-1750gs
+
+define Device/elecom_wrc-1750gsv
+  $(Device/elecom_wrc-gs)
+  IMAGE_SIZE := 11264k
+  DEVICE_MODEL := WRC-1750GSV
+  ELECOM_HWNAME := WRC-1750GSV
+endef
+TARGET_DEVICES += elecom_wrc-1750gsv
+
+define Device/elecom_wrc-1900gst
+  $(Device/elecom_wrc-gs)
+  IMAGE_SIZE := 11264k
+  DEVICE_MODEL := WRC-1900GST
+  ELECOM_HWNAME := WRC-1900GST
+endef
 TARGET_DEVICES += elecom_wrc-1900gst

 define Device/elecom_wrc-2533gst
-  $(Device/uimage-lzma-loader)
+  $(Device/elecom_wrc-gs)
  IMAGE_SIZE := 11264k
-  DEVICE_VENDOR := ELECOM
  DEVICE_MODEL := WRC-2533GST
-  IMAGES += factory.bin
-  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \
-	elecom-gst-factory WRC-2533GST 0.00
-  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware wpad-basic
+  ELECOM_HWNAME := WRC-2533GST
 endef
 TARGET_DEVICES += elecom_wrc-2533gst

 define Device/elecom_wrc-2533gst2
-  $(Device/uimage-lzma-loader)
+  $(Device/elecom_wrc-gs)
  IMAGE_SIZE := 24576k
-  DEVICE_VENDOR := ELECOM
  DEVICE_MODEL := WRC-2533GST2
-  IMAGES += factory.bin
-  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \
-	elecom-gst-factory WRC-2533GST2 0.00
-  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware wpad-basic
+  ELECOM_HWNAME := WRC-2533GST2
 endef
 TARGET_DEVICES += elecom_wrc-2533gst2

@ -511,21 +539,35 @@ define Device/lenovo_newifi-d1
 endef
 TARGET_DEVICES += lenovo_newifi-d1

-define Device/linksys_ea7500-v2
+define Device/linksys_ea7xxx
  $(Device/uimage-lzma-loader)
  BLOCKSIZE := 128k
  PAGESIZE := 2048
  KERNEL_SIZE := 4096k
  IMAGE_SIZE := 36864k
  DEVICE_VENDOR := Linksys
-  DEVICE_MODEL := EA7500
-  DEVICE_VARIANT := v2
-  DEVICE_PACKAGES := kmod-usb3 kmod-mt7615e kmod-mt7615-firmware wpad-basic uboot-envtools
+  DEVICE_PACKAGES := kmod-usb3 kmod-mt7615e kmod-mt7615-firmware wpad-basic \
+	uboot-envtools
  UBINIZE_OPTS := -E 5
  IMAGES := sysupgrade.bin factory.bin
  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata | check-size
  IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | \
-	append-ubi | check-size | linksys-image type=EA7500v2
+	append-ubi | check-size | linksys-image type=$$$$(LINKSYS_HWNAME)
+endef
+
+define Device/linksys_ea7300-v1
+  $(Device/linksys_ea7xxx)
+  DEVICE_MODEL := EA7300
+  DEVICE_VARIANT := v1
+  LINKSYS_HWNAME := EA7300
+endef
+TARGET_DEVICES += linksys_ea7300-v1
+
+define Device/linksys_ea7500-v2
+  $(Device/linksys_ea7xxx)
+  DEVICE_MODEL := EA7500
+  DEVICE_VARIANT := v2
+  LINKSYS_HWNAME := EA7500v2
 endef
 TARGET_DEVICES += linksys_ea7500-v2

--- a/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds
+++ b/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds
@ -26,7 +26,8 @@ d-team,pbr-m1|\
 gehua,ghl-r-001)
 	ucidef_set_led_netdev "internet" "internet" "$boardname:blue:internet" "wan"
 	;;
-dlink,dir-860l-b1)
+dlink,dir-860l-b1|\
+dlink,dir-878-a1)
 	ucidef_set_led_netdev "wan" "wan" "$boardname:green:net" "wan"
 	;;
 gnubee,gb-pc1|\
@ -34,6 +35,7 @@ gnubee,gb-pc2)
 	ucidef_set_led_netdev "lan1" "lan1" "$boardname:green:lan1" "lan1"
 	ucidef_set_led_netdev "lan2" "lan2" "$boardname:green:lan2" "lan2"
 	;;
+linksys,ea7300-v1|\
 linksys,ea7500-v2)
 	ucidef_set_led_netdev "lan1" "lan1 link" "$boardname:green:lan1" "lan1" "link"
 	ucidef_set_led_netdev "lan2" "lan2 link" "$boardname:green:lan2" "lan2" "link"
--- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network
+++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network
@ -106,6 +106,7 @@ ramips_setup_macs()
 		wan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr)
 		label_mac=$wan_mac
 		;;
+	linksys,ea7300-v1|\
 	linksys,ea7500-v2)
 		lan_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
 		wan_mac=$lan_mac
--- a/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac
+++ b/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac
@ -10,6 +10,7 @@ PHYNBR=${DEVPATH##*/phy}
 board=$(board_name)

 case "$board" in
+	linksys,ea7300-v1|\
 	linksys,ea7500-v2)
 		hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
 		[ "$PHYNBR" = "0" ] && macaddr_add $hw_mac_addr 1 > /sys${DEVPATH}/macaddress
--- a/target/linux/ramips/mt7621/base-files/etc/init.d/bootcount
+++ b/target/linux/ramips/mt7621/base-files/etc/init.d/bootcount
@ -8,6 +8,7 @@ boot() {
 		[ -n "$(fw_printenv bootcount bootchanged 2>/dev/null)" ] &&\
 			echo -e "bootcount\nbootchanged\n" | /usr/sbin/fw_setenv -s -
 		;;
+	linksys,ea7300-v1|\
 	linksys,ea7500-v2)
 		mtd resetbc s_env || true
 		;;
--- a/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh
@ -45,6 +45,7 @@ platform_do_upgrade() {
 	asus,rt-ac65p|\
 	asus,rt-ac85p|\
 	hiwifi,hc5962|\
+	linksys,ea7300-v1|\
 	linksys,ea7500-v2|\
 	netgear,r6220|\
 	netgear,r6260|\
--- a/toolchain/glibc/common.mk
+++ b/toolchain/glibc/common.mk
@ -11,8 +11,8 @@ PKG_VERSION:=2.31

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
-PKG_SOURCE_VERSION:=3a44844c97a8ca1d0798c45b5252e6a49f9cf8e1
-PKG_MIRROR_HASH:=d7206510e494b3c723173d8ec0dd2e41314da59075871c5642324688001b3f6e
+PKG_SOURCE_VERSION:=4e8a33a9590edc5c3a2cc5e726a3f2a73b66cdc0
+PKG_MIRROR_HASH:=41f678661dd1ee644dfae9734e27b47877ed7dee87c27eaddd9055394d36fe6a
 PKG_SOURCE_URL:=https://sourceware.org/git/glibc.git
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.xz