35dc676ba3
Drop upstreamed patches, refresh remaining patches. Signed-off-by: ZiMing Mo <msylgj@immortalwrt.org> [rebased upon HEAD] Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
90 lines
2.9 KiB
Diff
90 lines
2.9 KiB
Diff
From 1847729a77175ba5cd64adb419d15dca0f19eb48 Mon Sep 17 00:00:00 2001
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From: David Wu <david.wu@rock-chips.com>
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Date: Thu, 31 Dec 2020 18:34:12 +0800
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Subject: [PATCH] arm64: dts: rockchip: rk3568: Add xpcs support
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Change-Id: I431393b2346f5f7fd6b0d74f79e643df9a586479
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Signed-off-by: David Wu <david.wu@rock-chips.com>
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---
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arch/arm64/boot/dts/rockchip/rk3566.dtsi | 1 +
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 32 +++++++++++++++++++++---
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2 files changed, 29 insertions(+), 4 deletions(-)
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -222,6 +222,13 @@
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arm,no-tick-in-suspend;
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};
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+ gmac1_xpcsclk: xpcs-gmac1-clock {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ clock-output-names = "clk_gmac1_xpcs_mii";
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+ #clock-cells = <0>;
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+ };
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+
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xin24m: xin24m {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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@@ -376,6 +383,12 @@
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status = "disabled";
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};
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+ xpcs: syscon@fda00000 {
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+ compatible = "rockchip,rk3568-xpcs", "syscon";
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+ reg = <0x0 0xfda00000 0x0 0x200000>;
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+ status = "disabled";
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+ };
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+
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pmugrf: syscon@fdc20000 {
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compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
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reg = <0x0 0xfdc20000 0x0 0x10000>;
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@@ -675,11 +688,13 @@
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clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
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<&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
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<&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
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- <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
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+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
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+ <&cru PCLK_XPCS>;
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clock-names = "stmmaceth", "mac_clk_rx",
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"mac_clk_tx", "clk_mac_refout",
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"aclk_mac", "pclk_mac",
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- "clk_mac_speed", "ptp_ref";
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+ "clk_mac_speed", "ptp_ref",
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+ "pclk_xpcs";
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resets = <&cru SRST_A_GMAC1>;
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reset-names = "stmmaceth";
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rockchip,grf = <&grf>;
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--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -8,6 +8,13 @@
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/ {
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compatible = "rockchip,rk3568";
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+ gmac0_xpcsclk: xpcs-gmac0-clock {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ clock-output-names = "clk_gmac0_xpcs_mii";
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+ #clock-cells = <0>;
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+ };
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+
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sata0: sata@fc000000 {
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compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
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reg = <0 0xfc000000 0 0x1000>;
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@@ -175,11 +182,13 @@
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clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
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<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
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<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
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- <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
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+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
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+ <&cru PCLK_XPCS>;
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clock-names = "stmmaceth", "mac_clk_rx",
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"mac_clk_tx", "clk_mac_refout",
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"aclk_mac", "pclk_mac",
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- "clk_mac_speed", "ptp_ref";
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+ "clk_mac_speed", "ptp_ref",
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+ "pclk_xpcs";
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resets = <&cru SRST_A_GMAC0>;
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reset-names = "stmmaceth";
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rockchip,grf = <&grf>;
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