20ea6adbf1
Build system: x86_64 Build-tested: bcm2708, bcm2709, bcm2710, bcm2711 Run-tested: bcm2708/RPiB+, bcm2709/RPi3B, bcm2710/RPi3B, bcm2711/RPi4B Signed-off-by: Marty Jones <mj8263788@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
58 lines
1.7 KiB
Diff
58 lines
1.7 KiB
Diff
From 7971426f2462b02ea1bf12d902ca066e07eeb64b Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Wed, 26 May 2021 16:13:02 +0200
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Subject: [PATCH] drm/vc4: Increase the core clock based on HVS load
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Depending on a given HVS output (HVS to PixelValves) and input (planes
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attached to a channel) load, the HVS needs for the core clock to be
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raised above its boot time default.
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Failing to do so will result in a vblank timeout and a stalled display
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pipeline.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_drv.h | 1 +
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drivers/gpu/drm/vc4/vc4_kms.c | 13 +++++++++++++
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2 files changed, 14 insertions(+)
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -321,6 +321,7 @@ struct vc4_hvs {
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u32 __iomem *dlist;
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struct clk *core_clk;
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+ struct clk_request *core_req;
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/* Memory manager for CRTCs to allocate space in the display
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* list. Units are dwords.
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--- a/drivers/gpu/drm/vc4/vc4_kms.c
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+++ b/drivers/gpu/drm/vc4/vc4_kms.c
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@@ -391,6 +391,11 @@ static void vc4_atomic_commit_tail(struc
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new_hvs_state->core_clock_rate);
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core_req = clk_request_start(hvs->core_clk, core_rate);
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+ /*
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+ * And remove the previous one based on the HVS
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+ * requirements if any.
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+ */
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+ clk_request_done(hvs->core_req);
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}
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drm_atomic_helper_commit_modeset_disables(dev, state);
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@@ -418,6 +423,14 @@ static void vc4_atomic_commit_tail(struc
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drm_dbg(dev, "Running the core clock at %lu Hz\n",
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new_hvs_state->core_clock_rate);
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+ /*
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+ * Request a clock rate based on the current HVS
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+ * requirements.
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+ */
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+ hvs->core_req = clk_request_start(hvs->core_clk,
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+ new_hvs_state->core_clock_rate);
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+
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+ /* And drop the temporary request */
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clk_request_done(core_req);
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}
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}
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