20ea6adbf1
Build system: x86_64 Build-tested: bcm2708, bcm2709, bcm2710, bcm2711 Run-tested: bcm2708/RPiB+, bcm2709/RPi3B, bcm2710/RPi3B, bcm2711/RPi4B Signed-off-by: Marty Jones <mj8263788@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
267 lines
7.3 KiB
Diff
267 lines
7.3 KiB
Diff
From c16cebe5ebfb309074ff7cc9ddeaf37724d31512 Mon Sep 17 00:00:00 2001
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From: Daniel Scally <djrscally@gmail.com>
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Date: Tue, 15 Feb 2022 23:07:32 +0000
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Subject: [PATCH] media: i2c: Add ov7251_pll_configure()
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Rather than having the pll settings hidden inside mode blobs, define
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them in structs and use a dedicated function to set them. This makes
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it simpler to extend the driver to support other external clock
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frequencies.
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Signed-off-by: Daniel Scally <djrscally@gmail.com>
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---
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drivers/media/i2c/ov7251.c | 165 ++++++++++++++++++++++++++++++-------
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1 file changed, 135 insertions(+), 30 deletions(-)
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--- a/drivers/media/i2c/ov7251.c
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+++ b/drivers/media/i2c/ov7251.c
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@@ -42,6 +42,16 @@
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#define OV7251_TIMING_FORMAT2_MIRROR BIT(2)
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#define OV7251_PRE_ISP_00 0x5e00
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#define OV7251_PRE_ISP_00_TEST_PATTERN BIT(7)
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+#define OV7251_PLL1_PRE_DIV_REG 0x30b4
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+#define OV7251_PLL1_MULT_REG 0x30b3
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+#define OV7251_PLL1_DIVIDER_REG 0x30b1
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+#define OV7251_PLL1_PIX_DIV_REG 0x30b0
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+#define OV7251_PLL1_MIPI_DIV_REG 0x30b5
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+#define OV7251_PLL2_PRE_DIV_REG 0x3098
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+#define OV7251_PLL2_MULT_REG 0x3099
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+#define OV7251_PLL2_DIVIDER_REG 0x309d
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+#define OV7251_PLL2_SYS_DIV_REG 0x309a
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+#define OV7251_PLL2_ADC_DIV_REG 0x309b
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struct reg_value {
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u16 reg;
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@@ -60,6 +70,27 @@ struct ov7251_mode_info {
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struct v4l2_fract timeperframe;
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};
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+struct ov7251_pll1_config {
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+ unsigned int pre_div;
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+ unsigned int mult;
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+ unsigned int div;
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+ unsigned int pix_div;
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+ unsigned int mipi_div;
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+};
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+
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+struct ov7251_pll2_config {
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+ unsigned int pre_div;
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+ unsigned int mult;
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+ unsigned int div;
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+ unsigned int sys_div;
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+ unsigned int adc_div;
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+};
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+
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+struct ov7251_pll_configs {
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+ const struct ov7251_pll1_config *pll1;
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+ const struct ov7251_pll2_config *pll2;
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+};
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+
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struct ov7251 {
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struct i2c_client *i2c_client;
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struct device *dev;
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@@ -71,6 +102,8 @@ struct ov7251 {
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struct clk *xclk;
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u32 xclk_freq;
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+ const struct ov7251_pll_configs *pll_configs;
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+
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struct regulator *io_regulator;
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struct regulator *core_regulator;
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struct regulator *analog_regulator;
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@@ -100,6 +133,36 @@ static inline struct ov7251 *to_ov7251(s
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return container_of(sd, struct ov7251, sd);
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}
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+enum xclk_rate {
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+ OV7251_24_MHZ,
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+ OV7251_NUM_SUPPORTED_RATES
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+};
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+
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+static const struct ov7251_pll1_config ov7251_pll1_config_24_mhz = {
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+ .pre_div = 0x03,
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+ .mult = 0x64,
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+ .div = 0x01,
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+ .pix_div = 0x0a,
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+ .mipi_div = 0x05
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+};
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+
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+static const struct ov7251_pll2_config ov7251_pll2_config_24_mhz = {
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+ .pre_div = 0x04,
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+ .mult = 0x28,
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+ .div = 0x00,
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+ .sys_div = 0x05,
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+ .adc_div = 0x04
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+};
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+
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+static const struct ov7251_pll_configs ov7251_pll_configs_24_mhz = {
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+ .pll1 = &ov7251_pll1_config_24_mhz,
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+ .pll2 = &ov7251_pll2_config_24_mhz
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+};
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+
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+static const struct ov7251_pll_configs *ov7251_pll_configs[] = {
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+ [OV7251_24_MHZ] = &ov7251_pll_configs_24_mhz
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+};
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+
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static const struct reg_value ov7251_global_init_setting[] = {
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{ 0x0103, 0x01 },
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{ 0x303b, 0x02 },
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@@ -118,16 +181,6 @@ static const struct reg_value ov7251_set
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{ 0x301c, 0xf0 },
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{ 0x3023, 0x05 },
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{ 0x3037, 0xf0 },
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- { 0x3098, 0x04 }, /* pll2 pre divider */
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- { 0x3099, 0x28 }, /* pll2 multiplier */
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- { 0x309a, 0x05 }, /* pll2 sys divider */
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- { 0x309b, 0x04 }, /* pll2 adc divider */
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- { 0x309d, 0x00 }, /* pll2 divider */
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- { 0x30b0, 0x0a }, /* pll1 pix divider */
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- { 0x30b1, 0x01 }, /* pll1 divider */
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- { 0x30b3, 0x64 }, /* pll1 multiplier */
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- { 0x30b4, 0x03 }, /* pll1 pre divider */
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- { 0x30b5, 0x05 }, /* pll1 mipi divider */
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{ 0x3106, 0xda },
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{ 0x3503, 0x07 },
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{ 0x3509, 0x10 },
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@@ -256,16 +309,6 @@ static const struct reg_value ov7251_set
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{ 0x301c, 0x00 },
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{ 0x3023, 0x05 },
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{ 0x3037, 0xf0 },
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- { 0x3098, 0x04 }, /* pll2 pre divider */
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- { 0x3099, 0x28 }, /* pll2 multiplier */
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- { 0x309a, 0x05 }, /* pll2 sys divider */
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- { 0x309b, 0x04 }, /* pll2 adc divider */
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- { 0x309d, 0x00 }, /* pll2 divider */
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- { 0x30b0, 0x0a }, /* pll1 pix divider */
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- { 0x30b1, 0x01 }, /* pll1 divider */
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- { 0x30b3, 0x64 }, /* pll1 multiplier */
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- { 0x30b4, 0x03 }, /* pll1 pre divider */
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- { 0x30b5, 0x05 }, /* pll1 mipi divider */
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{ 0x3106, 0xda },
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{ 0x3503, 0x07 },
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{ 0x3509, 0x10 },
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@@ -394,16 +437,6 @@ static const struct reg_value ov7251_set
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{ 0x301c, 0x00 },
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{ 0x3023, 0x05 },
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{ 0x3037, 0xf0 },
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- { 0x3098, 0x04 }, /* pll2 pre divider */
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- { 0x3099, 0x28 }, /* pll2 multiplier */
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- { 0x309a, 0x05 }, /* pll2 sys divider */
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- { 0x309b, 0x04 }, /* pll2 adc divider */
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- { 0x309d, 0x00 }, /* pll2 divider */
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- { 0x30b0, 0x0a }, /* pll1 pix divider */
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- { 0x30b1, 0x01 }, /* pll1 divider */
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- { 0x30b3, 0x64 }, /* pll1 multiplier */
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- { 0x30b4, 0x03 }, /* pll1 pre divider */
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- { 0x30b5, 0x05 }, /* pll1 mipi divider */
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{ 0x3106, 0xda },
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{ 0x3503, 0x07 },
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{ 0x3509, 0x10 },
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@@ -519,6 +552,10 @@ static const struct reg_value ov7251_set
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{ 0x5001, 0x80 },
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};
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+static const unsigned long supported_xclk_rates[] = {
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+ [OV7251_24_MHZ] = 24000000,
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+};
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+
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static const s64 link_freq[] = {
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240000000,
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};
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@@ -692,6 +729,63 @@ static int ov7251_read_reg(struct ov7251
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return 0;
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}
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+static int ov7251_pll_configure(struct ov7251 *ov7251)
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+{
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+ const struct ov7251_pll_configs *configs;
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+ int ret;
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+
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+ configs = ov7251->pll_configs;
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+
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+ ret = ov7251_write_reg(ov7251, OV7251_PLL1_PRE_DIV_REG,
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+ configs->pll1->pre_div);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = ov7251_write_reg(ov7251, OV7251_PLL1_MULT_REG,
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+ configs->pll1->mult);
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+ if (ret < 0)
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+ return ret;
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+ ret = ov7251_write_reg(ov7251, OV7251_PLL1_DIVIDER_REG,
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+ configs->pll1->div);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = ov7251_write_reg(ov7251, OV7251_PLL1_PIX_DIV_REG,
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+ configs->pll1->pix_div);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = ov7251_write_reg(ov7251, OV7251_PLL1_MIPI_DIV_REG,
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+ configs->pll1->mipi_div);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = ov7251_write_reg(ov7251, OV7251_PLL2_PRE_DIV_REG,
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+ configs->pll2->pre_div);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = ov7251_write_reg(ov7251, OV7251_PLL2_MULT_REG,
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+ configs->pll2->mult);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = ov7251_write_reg(ov7251, OV7251_PLL2_DIVIDER_REG,
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+ configs->pll2->div);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = ov7251_write_reg(ov7251, OV7251_PLL2_SYS_DIV_REG,
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+ configs->pll2->sys_div);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = ov7251_write_reg(ov7251, OV7251_PLL2_ADC_DIV_REG,
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+ configs->pll2->adc_div);
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+
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+ return ret;
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+}
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+
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static int ov7251_set_exposure(struct ov7251 *ov7251, s32 exposure)
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{
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u16 reg;
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@@ -1143,6 +1237,11 @@ static int ov7251_s_stream(struct v4l2_s
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mutex_lock(&ov7251->lock);
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if (enable) {
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+ ret = ov7251_pll_configure(ov7251);
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+ if (ret)
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+ return dev_err_probe(ov7251->dev, ret,
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+ "error configuring PLLs\n");
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+
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ret = ov7251_set_register_array(ov7251,
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ov7251->current_mode->data,
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ov7251->current_mode->data_size);
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@@ -1326,6 +1425,7 @@ static int ov7251_probe(struct i2c_clien
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struct ov7251 *ov7251;
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u8 chip_id_high, chip_id_low, chip_rev;
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int ret;
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+ int i;
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ov7251 = devm_kzalloc(dev, sizeof(struct ov7251), GFP_KERNEL);
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if (!ov7251)
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@@ -1364,6 +1464,11 @@ static int ov7251_probe(struct i2c_clien
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dev_err(dev, "could not set xclk frequency\n");
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return ret;
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}
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+ for (i = 0; i < ARRAY_SIZE(supported_xclk_rates); i++)
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+ if (ov7251->xclk_freq == supported_xclk_rates[i])
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+ break;
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+
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+ ov7251->pll_configs = ov7251_pll_configs[i];
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ov7251->io_regulator = devm_regulator_get(dev, "vdddo");
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if (IS_ERR(ov7251->io_regulator)) {
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