20ea6adbf1
Build system: x86_64 Build-tested: bcm2708, bcm2709, bcm2710, bcm2711 Run-tested: bcm2708/RPiB+, bcm2709/RPi3B, bcm2710/RPi3B, bcm2711/RPi4B Signed-off-by: Marty Jones <mj8263788@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
59 lines
2.1 KiB
Diff
59 lines
2.1 KiB
Diff
From 9d71b0d4e30692d0d186352b494ef4e70234ca7c Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Fri, 25 Mar 2022 17:09:41 +0100
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Subject: [PATCH] drm/vc4: Make sure we don't end up with a core clock
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too high
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Following the clock rate range improvements to the clock framework,
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trying to set a disjoint range on a clock will now result in an error.
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Thus, we can't set a minimum rate higher than the maximum reported by
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the firmware, or clk_set_min_rate() will fail.
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Thus we need to clamp the rate we are about to ask for to the maximum
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rate possible on that clock.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_kms.c | 14 +++++++++-----
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1 file changed, 9 insertions(+), 5 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_kms.c
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+++ b/drivers/gpu/drm/vc4/vc4_kms.c
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@@ -354,6 +354,7 @@ static void vc4_atomic_commit_tail(struc
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struct vc4_hvs_state *new_hvs_state;
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struct drm_crtc *crtc;
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struct vc4_hvs_state *old_hvs_state;
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+ unsigned long max_clock_rate = clk_get_max_rate(hvs->core_clk);
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unsigned int channel;
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int i;
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@@ -397,8 +398,8 @@ static void vc4_atomic_commit_tail(struc
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if (vc4->hvs && vc4->hvs->hvs5) {
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unsigned long state_rate = max(old_hvs_state->core_clock_rate,
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new_hvs_state->core_clock_rate);
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- unsigned long core_rate = max_t(unsigned long,
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- 500000000, state_rate);
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+ unsigned long core_rate = clamp_t(unsigned long, state_rate,
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+ 500000000, max_clock_rate);
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WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));
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}
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@@ -427,10 +428,13 @@ static void vc4_atomic_commit_tail(struc
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drm_atomic_helper_cleanup_planes(dev, state);
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if (vc4->hvs && vc4->hvs->hvs5) {
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- drm_dbg(dev, "Running the core clock at %lu Hz\n",
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- new_hvs_state->core_clock_rate);
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+ unsigned long core_rate = min_t(unsigned long,
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+ max_clock_rate,
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+ new_hvs_state->core_clock_rate);
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+
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+ drm_dbg(dev, "Running the core clock at %lu Hz\n", core_rate);
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- WARN_ON(clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate));
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+ WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));
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drm_dbg(dev, "Core clock actual rate: %lu Hz\n",
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clk_get_rate(hvs->core_clk));
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