![Daniel Golle](/assets/img/avatar_default.png)
Instead of dropping *fix-typo-in-__mtk_foe_entry.patch which effectively means keeping the (also wrong) assignment of MTK_FOE_STATE_BIND, rather use MTK_FOE_STATE_INVALID as that works well on both older (NETSYS_V1) and newer (NETSYS_V2) MediaTek SoCs. Suggested-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
190 lines
5.9 KiB
Diff
190 lines
5.9 KiB
Diff
From e5ecb4f619197b93fa682d722452dc8412864cdb Mon Sep 17 00:00:00 2001
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Message-Id: <e5ecb4f619197b93fa682d722452dc8412864cdb.1662886033.git.lorenzo@kernel.org>
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Fri, 26 Aug 2022 01:12:57 +0200
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Subject: [PATCH net-next 1/5] net: ethernet: mtk_eth_wed: add
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mtk_wed_configure_irq and mtk_wed_dma_{enable/disable}
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Introduce mtk_wed_configure_irq, mtk_wed_dma_enable and mtk_wed_dma_disable
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utility routines.
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This is a preliminary patch to introduce mt7986 wed support.
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Co-developed-by: Bo Jiao <Bo.Jiao@mediatek.com>
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Signed-off-by: Bo Jiao <Bo.Jiao@mediatek.com>
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Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
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Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_wed.c | 87 +++++++++++++-------
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drivers/net/ethernet/mediatek/mtk_wed_regs.h | 6 +-
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2 files changed, 64 insertions(+), 29 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_wed.c
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+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
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@@ -237,9 +237,30 @@ mtk_wed_set_ext_int(struct mtk_wed_devic
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}
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static void
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-mtk_wed_stop(struct mtk_wed_device *dev)
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+mtk_wed_dma_disable(struct mtk_wed_device *dev)
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{
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+ wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
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+ MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
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+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
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+
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+ wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
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+
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+ wed_clr(dev, MTK_WED_GLO_CFG,
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+ MTK_WED_GLO_CFG_TX_DMA_EN |
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+ MTK_WED_GLO_CFG_RX_DMA_EN);
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+
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regmap_write(dev->hw->mirror, dev->hw->index * 4, 0);
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+ wdma_m32(dev, MTK_WDMA_GLO_CFG,
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+ MTK_WDMA_GLO_CFG_TX_DMA_EN |
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+ MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
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+ MTK_WDMA_GLO_CFG_RX_INFO2_PRERES |
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+ MTK_WDMA_GLO_CFG_RX_INFO3_PRERES, 0);
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+}
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+
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+static void
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+mtk_wed_stop(struct mtk_wed_device *dev)
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+{
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+ mtk_wed_dma_disable(dev);
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mtk_wed_set_ext_int(dev, false);
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wed_clr(dev, MTK_WED_CTRL,
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@@ -252,15 +273,6 @@ mtk_wed_stop(struct mtk_wed_device *dev)
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wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
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wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
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wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
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-
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- wed_clr(dev, MTK_WED_GLO_CFG,
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- MTK_WED_GLO_CFG_TX_DMA_EN |
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- MTK_WED_GLO_CFG_RX_DMA_EN);
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- wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
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- MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
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- MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
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- wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
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- MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
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}
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static void
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@@ -313,7 +325,10 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
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MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
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wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
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- wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_INFO_PRERES);
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+ wdma_set(dev, MTK_WDMA_GLO_CFG,
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+ MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
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+ MTK_WDMA_GLO_CFG_RX_INFO2_PRERES |
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+ MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
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offset = dev->hw->index ? 0x04000400 : 0;
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wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);
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@@ -520,43 +535,38 @@ mtk_wed_wdma_ring_setup(struct mtk_wed_d
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}
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static void
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-mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
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+mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask)
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{
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- u32 wdma_mask;
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- u32 val;
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- int i;
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-
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- for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
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- if (!dev->tx_wdma[i].desc)
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- mtk_wed_wdma_ring_setup(dev, i, 16);
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-
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- wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));
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-
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- mtk_wed_hw_init(dev);
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+ u32 wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));
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+ /* wed control cr set */
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wed_set(dev, MTK_WED_CTRL,
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MTK_WED_CTRL_WDMA_INT_AGENT_EN |
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MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
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MTK_WED_CTRL_WED_TX_BM_EN |
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MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
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- wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, MTK_WED_PCIE_INT_TRIGGER_STATUS);
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+ wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
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+ MTK_WED_PCIE_INT_TRIGGER_STATUS);
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wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER,
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MTK_WED_WPDMA_INT_TRIGGER_RX_DONE |
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MTK_WED_WPDMA_INT_TRIGGER_TX_DONE);
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- wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
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- MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
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-
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+ /* initail wdma interrupt agent */
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wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);
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wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
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wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask);
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wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask);
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-
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wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
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wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
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+}
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+
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+static void
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+mtk_wed_dma_enable(struct mtk_wed_device *dev)
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+{
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+ wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
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wed_set(dev, MTK_WED_GLO_CFG,
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MTK_WED_GLO_CFG_TX_DMA_EN |
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@@ -567,6 +577,26 @@ mtk_wed_start(struct mtk_wed_device *dev
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wed_set(dev, MTK_WED_WDMA_GLO_CFG,
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MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
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+ wdma_set(dev, MTK_WDMA_GLO_CFG,
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+ MTK_WDMA_GLO_CFG_TX_DMA_EN |
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+ MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
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+ MTK_WDMA_GLO_CFG_RX_INFO2_PRERES |
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+ MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
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+}
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+
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+static void
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+mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
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+{
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+ u32 val;
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
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+ if (!dev->tx_wdma[i].desc)
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+ mtk_wed_wdma_ring_setup(dev, i, 16);
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+
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+ mtk_wed_hw_init(dev);
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+ mtk_wed_configure_irq(dev, irq_mask);
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+
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mtk_wed_set_ext_int(dev, true);
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val = dev->wlan.wpdma_phys |
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MTK_PCIE_MIRROR_MAP_EN |
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@@ -577,6 +607,7 @@ mtk_wed_start(struct mtk_wed_device *dev
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val |= BIT(0);
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regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
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+ mtk_wed_dma_enable(dev);
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dev->running = true;
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}
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--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
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+++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
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@@ -224,7 +224,11 @@ struct mtk_wdma_desc {
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#define MTK_WDMA_RING_RX(_n) (0x100 + (_n) * 0x10)
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#define MTK_WDMA_GLO_CFG 0x204
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-#define MTK_WDMA_GLO_CFG_RX_INFO_PRERES GENMASK(28, 26)
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+#define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0)
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+#define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2)
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+#define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26)
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+#define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27)
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+#define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28)
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#define MTK_WDMA_RESET_IDX 0x208
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#define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0)
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