2f663cab46
Replace patches for MediaTek Ethernet driver SGMII/SerDes unit with their corresponding upstream patches. Not all of the patches in our tree went upstream as-is, some are slightly different implementations, and they require the phylink_pcs helpers now made available. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
64 lines
2.3 KiB
Diff
64 lines
2.3 KiB
Diff
From 3027d89f87707e7f3e5b683e0d37a32afb5bde96 Mon Sep 17 00:00:00 2001
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From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
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Date: Thu, 27 Oct 2022 14:11:23 +0100
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Subject: [PATCH 09/10] net: mtk_eth_soc: move and correct link timer
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programming
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Program the link timer appropriately for the interface mode being
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used, using the newly introduced phylink helper that provides the
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nanosecond link timer interval.
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The intervals are 1.6ms for SGMII based protocols and 10ms for
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802.3z based protocols.
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_sgmii.c | 13 ++++++++-----
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1 file changed, 8 insertions(+), 5 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -36,10 +36,6 @@ static void mtk_pcs_get_state(struct phy
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/* For SGMII interface mode */
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static void mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
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{
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- /* Setup the link timer and QPHY power up inside SGMIISYS */
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- regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
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- SGMII_LINK_TIMER_DEFAULT);
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-
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regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
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SGMII_REMOTE_FAULT_DIS, SGMII_REMOTE_FAULT_DIS);
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@@ -69,8 +65,8 @@ static int mtk_pcs_config(struct phylink
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bool permit_pause_to_mac)
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{
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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+ int advertise, link_timer;
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unsigned int rgc3;
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- int advertise;
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bool changed;
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
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@@ -83,6 +79,10 @@ static int mtk_pcs_config(struct phylink
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if (advertise < 0)
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return advertise;
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+ link_timer = phylink_get_link_timer_ns(interface);
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+ if (link_timer < 0)
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+ return link_timer;
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+
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/* Configure the underlying interface speed */
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regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
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RG_PHY_SPEED_3_125G, rgc3);
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@@ -91,6 +91,9 @@ static int mtk_pcs_config(struct phylink
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regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
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SGMII_ADVERTISE, advertise, &changed);
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+ /* Setup the link timer and QPHY power up inside SGMIISYS */
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+ regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, link_timer / 2 / 8);
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+
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/* Setup SGMIISYS with the determined property */
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if (interface != PHY_INTERFACE_MODE_SGMII)
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mtk_pcs_setup_mode_force(mpcs, interface);
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