This commit is contained in:
coolsnowwolf 2017-09-12 01:07:20 +08:00
parent c6482e5076
commit 03efb03919
122 changed files with 564 additions and 20059 deletions

1
.gitattributes vendored Normal file
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@ -0,0 +1 @@
* -text

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@ -112,6 +112,19 @@ config KERNEL_DEBUG_INFO
help
This will compile your kernel and modules with debug information.
config KERNEL_DEBUG_LL_UART_NONE
bool
default n
depends on arm
config KERNEL_DEBUG_LL
bool
default n
depends on arm
select KERNEL_DEBUG_LL_UART_NONE
help
ARM low level debugging.
config KERNEL_DYNAMIC_DEBUG
bool "Compile the kernel with dynamic printk"
select KERNEL_DEBUG_FS

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@ -41,7 +41,8 @@ endef
# 1: destination file
define FeedSourcesAppend
( \
echo "src/gz %n_core %U/targets/%S/packages"; \
echo "src/gz %n_custom http://lede-ac58u.zyxmon.org/packages"; \
echo "# src/gz %n_core %U/targets/%S/packages"; \
$(strip $(if $(CONFIG_PER_FEED_REPO), \
$(foreach feed,base $(FEEDS_ENABLED),echo "src/gz %n_$(feed) %U/packages/%A/$(feed)";) \
$(if $(CONFIG_PER_FEED_REPO_ADD_DISABLED), \

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@ -3,12 +3,12 @@
LINUX_RELEASE?=1
LINUX_VERSION-3.18 = .43
LINUX_VERSION-4.4 = .85
LINUX_VERSION-4.9 = .47
LINUX_VERSION-4.4 = .87
LINUX_VERSION-4.9 = .49
LINUX_KERNEL_HASH-3.18.43 = 1236e8123a6ce537d5029232560966feed054ae31776fe8481dd7d18cdd5492c
LINUX_KERNEL_HASH-4.4.85 = cfa49f631587e4587ba04236ce0e56765ea938c26815d5a29eec561b21d0f055
LINUX_KERNEL_HASH-4.9.47 = 75be9679d69460a45e77a61474a6d8eee34de21b9929fe4992971dff122541c9
LINUX_KERNEL_HASH-4.4.87 = 1ab05222c3c55e062c3f7418976137ee529f92174261ccb0cd5a7d3370ff6f5b
LINUX_KERNEL_HASH-4.9.49 = 57ecdcf180b56356b2e15264ca567a8fcd9eec993fc70286bec3bd0005e791fb
ifdef KERNEL_PATCHVER
LINUX_VERSION:=$(KERNEL_PATCHVER)$(strip $(LINUX_VERSION-$(KERNEL_PATCHVER)))

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@ -19,7 +19,7 @@ luci-app-filetransfer luci-app-shadowsocksr-pro
# For nas targets
DEFAULT_PACKAGES.nas:=block-mount fdisk lsblk mdadm
# For router targets
DEFAULT_PACKAGES.router:=block-mount dnsmasq-full iptables ip6tables ppp ppp-mod-pppoe firewall odhcpd odhcp6c
DEFAULT_PACKAGES.router:=dnsmasq-full iptables ip6tables ppp ppp-mod-pppoe firewall odhcpd odhcp6c
DEFAULT_PACKAGES.bootloader:=
ifneq ($(DUMP),)

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@ -10,9 +10,9 @@ include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=strace
PKG_VERSION:=4.16
PKG_VERSION:=4.19
PKG_RELEASE:=1
PKG_HASH:=98487cb5178ec1259986cc9f6e2a844f50e5d1208c112cc22431a1e4d9adf0ef
PKG_HASH:=7c93ebc6c29280f47c24a0eb86873a99ccb2cac6512c60a60ba4ef99ab807281
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@SF/$(PKG_NAME)

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@ -248,7 +248,7 @@ define Package/ath10k-firmware-qca4019/install
$(PKG_BUILD_DIR)/QCA4019/hw1.0/board-2.bin \
$(1)/lib/firmware/ath10k/QCA4019/hw1.0/
$(INSTALL_DATA) \
$(PKG_BUILD_DIR)/QCA4019/hw1.0/3.4/firmware-5.bin_10.4-3.4-00082 \
$(PKG_BUILD_DIR)/QCA4019/hw1.0/3.2.1/firmware-5.bin_10.4-3.2.1-00053 \
$(1)/lib/firmware/ath10k/QCA4019/hw1.0/firmware-5.bin
endef

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@ -1009,18 +1009,3 @@ define KernelPackage/mdio/description
endef
$(eval $(call KernelPackage,mdio))
define KernelPackage/macsec
SUBMENU:=$(NETWORK_SUPPORT_MENU)
TITLE:=IEEE 802.1AE MAC-level encryption (MAC)
DEPENDS:=+kmod-crypto-gcm @!LINUX_3_18 @!LINUX_4_4
KCONFIG:=CONFIG_MACSEC
FILES:=$(LINUX_DIR)/drivers/net/macsec.ko
AUTOLOAD:=$(call AutoLoad,13,macsec)
endef
define KernelPackage/macsec/description
MACsec is an encryption standard for Ethernet.
endef
$(eval $(call KernelPackage,macsec))

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@ -116,7 +116,7 @@ detect_mac80211() {
set wireless.radio${devidx}.hwmode=11${mode_band}
${dev_id}
${ht_capab}
set wireless.radio${devidx}.noscan=1
set wireless.radio${devidx}.disabled=1
set wireless.default_radio${devidx}=wifi-iface
set wireless.default_radio${devidx}.device=radio${devidx}

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@ -1,58 +0,0 @@
From f35a7f91f66af528b3ee1921de16bea31d347ab0 Mon Sep 17 00:00:00 2001
From: Rakesh Pillai <pillair@qti.qualcomm.com>
Date: Wed, 2 Aug 2017 16:03:37 +0530
Subject: ath10k: fix memory leak in rx ring buffer allocation
The rx ring buffers are added to a hash table if
firmware support full rx reorder. If the full rx
reorder support flag is not set before allocating
the rx ring buffers, none of the buffers are added
to the hash table.
There is a race condition between rx ring refill and
rx buffer replenish from napi poll. The interrupts are
enabled in hif start, before the rx ring is refilled during init.
We replenish buffers from napi poll due to the interrupts which
get enabled after hif start. Hence before the entire rx ring is
refilled during the init, the napi poll replenishes a few buffers
in steps of 100 buffers per attempt. During this rx ring replenish
from napi poll, the rx reorder flag has not been set due to which
the replenished buffers are not added to the hash table
Set the rx full reorder support flag before we allocate
the rx ring buffer to avoid the memory leak.
Signed-off-by: Rakesh Pillai <pillair@qti.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
---
drivers/net/wireless/ath/ath10k/core.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
--- a/drivers/net/wireless/ath/ath10k/core.c
+++ b/drivers/net/wireless/ath/ath10k/core.c
@@ -1957,6 +1957,12 @@ int ath10k_core_start(struct ath10k *ar,
goto err_wmi_detach;
}
+ /* If firmware indicates Full Rx Reorder support it must be used in a
+ * slightly different manner. Let HTT code know.
+ */
+ ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
+ ar->wmi.svc_map));
+
status = ath10k_htt_rx_alloc(&ar->htt);
if (status) {
ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
@@ -2065,12 +2071,6 @@ int ath10k_core_start(struct ath10k *ar,
goto err_hif_stop;
}
- /* If firmware indicates Full Rx Reorder support it must be used in a
- * slightly different manner. Let HTT code know.
- */
- ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
- ar->wmi.svc_map));
-
status = ath10k_htt_rx_ring_refill(ar);
if (status) {
ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);

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@ -1,180 +0,0 @@
From a4aab099cc9e7c4c94b8a0973b2a483c69b541e3 Mon Sep 17 00:00:00 2001
From: Mohammed Shafi Shajakhan <mohammed@qti.qualcomm.com>
Date: Mon, 10 Apr 2017 21:08:17 +0530
Subject: ath10k: fix spectral scan for QCA99X0 family of chipsets
spectral_bin length (number of bins per fft sample) is usually
a value where (2^n = value), n is an integer. All of the QCA99X0
family of chipsets seems to report a spectral_bin length of
2^n + 'm' bytes, where m = 4, 12 based on the chipset. This 'm'
bytes seems to carry some radar related info which is currently
discarded only for 'bin_len = 68' bytes. Extend this discarding of
irrelevant 'bin_len' for QCA9984, QCA9888, IPQ4019 as well by
introducing a hardware parameter 'spectral_bin_discard'. Also
for QCA988X based family of chipsets which doesn't seem to have this
issue and also for some of the hardware which I have not tested
like QCA6174/QCA9377 the existing behaviour is retained as it is.
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qti.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
---
drivers/net/wireless/ath/ath10k/core.c | 12 ++++++++++++
drivers/net/wireless/ath/ath10k/hw.h | 3 +++
drivers/net/wireless/ath/ath10k/spectral.c | 26 +++++++++++++++++---------
3 files changed, 32 insertions(+), 9 deletions(-)
--- a/drivers/net/wireless/ath/ath10k/core.c
+++ b/drivers/net/wireless/ath/ath10k/core.c
@@ -71,6 +71,7 @@ static const struct ath10k_hw_params ath
},
.hw_ops = &qca988x_ops,
.decap_align_bytes = 4,
+ .spectral_bin_discard = 0,
},
{
.id = QCA9887_HW_1_0_VERSION,
@@ -91,6 +92,7 @@ static const struct ath10k_hw_params ath
},
.hw_ops = &qca988x_ops,
.decap_align_bytes = 4,
+ .spectral_bin_discard = 0,
},
{
.id = QCA6174_HW_2_1_VERSION,
@@ -110,6 +112,7 @@ static const struct ath10k_hw_params ath
},
.hw_ops = &qca988x_ops,
.decap_align_bytes = 4,
+ .spectral_bin_discard = 0,
},
{
.id = QCA6174_HW_2_1_VERSION,
@@ -129,6 +132,7 @@ static const struct ath10k_hw_params ath
},
.hw_ops = &qca988x_ops,
.decap_align_bytes = 4,
+ .spectral_bin_discard = 0,
},
{
.id = QCA6174_HW_3_0_VERSION,
@@ -148,6 +152,7 @@ static const struct ath10k_hw_params ath
},
.hw_ops = &qca988x_ops,
.decap_align_bytes = 4,
+ .spectral_bin_discard = 0,
},
{
.id = QCA6174_HW_3_2_VERSION,
@@ -168,6 +173,7 @@ static const struct ath10k_hw_params ath
},
.hw_ops = &qca988x_ops,
.decap_align_bytes = 4,
+ .spectral_bin_discard = 0,
},
{
.id = QCA99X0_HW_2_0_DEV_VERSION,
@@ -193,6 +199,7 @@ static const struct ath10k_hw_params ath
.sw_decrypt_mcast_mgmt = true,
.hw_ops = &qca99x0_ops,
.decap_align_bytes = 1,
+ .spectral_bin_discard = 4,
},
{
.id = QCA9984_HW_1_0_DEV_VERSION,
@@ -219,6 +226,7 @@ static const struct ath10k_hw_params ath
.sw_decrypt_mcast_mgmt = true,
.hw_ops = &qca99x0_ops,
.decap_align_bytes = 1,
+ .spectral_bin_discard = 12,
},
{
.id = QCA9888_HW_2_0_DEV_VERSION,
@@ -244,6 +252,7 @@ static const struct ath10k_hw_params ath
.sw_decrypt_mcast_mgmt = true,
.hw_ops = &qca99x0_ops,
.decap_align_bytes = 1,
+ .spectral_bin_discard = 12,
},
{
.id = QCA9377_HW_1_0_DEV_VERSION,
@@ -263,6 +272,7 @@ static const struct ath10k_hw_params ath
},
.hw_ops = &qca988x_ops,
.decap_align_bytes = 4,
+ .spectral_bin_discard = 0,
},
{
.id = QCA9377_HW_1_1_DEV_VERSION,
@@ -282,6 +292,7 @@ static const struct ath10k_hw_params ath
},
.hw_ops = &qca988x_ops,
.decap_align_bytes = 4,
+ .spectral_bin_discard = 0,
},
{
.id = QCA4019_HW_1_0_DEV_VERSION,
@@ -308,6 +319,7 @@ static const struct ath10k_hw_params ath
.sw_decrypt_mcast_mgmt = true,
.hw_ops = &qca99x0_ops,
.decap_align_bytes = 1,
+ .spectral_bin_discard = 4,
},
};
--- a/drivers/net/wireless/ath/ath10k/hw.h
+++ b/drivers/net/wireless/ath/ath10k/hw.h
@@ -391,6 +391,9 @@ struct ath10k_hw_params {
*/
u32 max_probe_resp_desc_thres;
+ /* Number of bytes to be discarded for each FFT sample */
+ int spectral_bin_discard;
+
u32 tx_chain_mask;
u32 rx_chain_mask;
u32 max_spatial_stream;
--- a/drivers/net/wireless/ath/ath10k/spectral.c
+++ b/drivers/net/wireless/ath/ath10k/spectral.c
@@ -56,6 +56,21 @@ static uint8_t get_max_exp(s8 max_index,
return max_exp;
}
+static inline size_t ath10k_spectral_fix_bin_size(struct ath10k *ar,
+ size_t bin_len)
+{
+ /* some chipsets reports bin size as 2^n bytes + 'm' bytes in
+ * report mode 2. First 2^n bytes carries inband tones and last
+ * 'm' bytes carries band edge detection data mainly used in
+ * radar detection purpose. Strip last 'm' bytes to make bin size
+ * as a valid one. 'm' can take possible values of 4, 12.
+ */
+ if (!is_power_of_2(bin_len))
+ bin_len -= ar->hw_params.spectral_bin_discard;
+
+ return bin_len;
+}
+
int ath10k_spectral_process_fft(struct ath10k *ar,
struct wmi_phyerr_ev_arg *phyerr,
const struct phyerr_fft_report *fftr,
@@ -70,18 +85,11 @@ int ath10k_spectral_process_fft(struct a
fft_sample = (struct fft_sample_ath10k *)&buf;
+ bin_len = ath10k_spectral_fix_bin_size(ar, bin_len);
+
if (bin_len < 64 || bin_len > SPECTRAL_ATH10K_MAX_NUM_BINS)
return -EINVAL;
- /* qca99x0 reports bin size as 68 bytes (64 bytes + 4 bytes) in
- * report mode 2. First 64 bytes carries inband tones (-32 to +31)
- * and last 4 byte carries band edge detection data (+32) mainly
- * used in radar detection purpose. Strip last 4 byte to make bin
- * size is valid one.
- */
- if (bin_len == 68)
- bin_len -= 4;
-
reg0 = __le32_to_cpu(fftr->reg0);
reg1 = __le32_to_cpu(fftr->reg1);

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@ -14,7 +14,7 @@ Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
--- a/drivers/net/wireless/ath/ath10k/core.c
+++ b/drivers/net/wireless/ath/ath10k/core.c
@@ -2341,6 +2341,16 @@ int ath10k_core_register(struct ath10k *
@@ -2329,6 +2329,16 @@ int ath10k_core_register(struct ath10k *
ar->chip_id = chip_id;
queue_work(ar->workqueue, &ar->register_work);

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@ -1,6 +1,6 @@
--- a/drivers/net/wireless/ath/ath10k/core.c
+++ b/drivers/net/wireless/ath/ath10k/core.c
@@ -703,7 +703,7 @@ static int ath10k_core_get_board_id_from
@@ -691,7 +691,7 @@ static int ath10k_core_get_board_id_from
if (ret) {
ath10k_err(ar, "could not execute otp for board id check: %d\n",
ret);

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@ -96,7 +96,7 @@ endef
define KernelPackage/mt7603/install
$(INSTALL_DIR) $(1)/lib/firmware
cp $(if $(CONFIG_TARGET_ramips_mt7628)$(CONFIG_TARGET_ramips_mt7688), \
cp $(if $(CONFIG_TARGET_ramips_mt76x8), \
$(PKG_BUILD_DIR)/firmware/mt7628_e1.bin \
$(PKG_BUILD_DIR)/firmware/mt7628_e2.bin \
,\

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@ -8,13 +8,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=mbedtls
PKG_VERSION:=2.5.1
PKG_VERSION:=2.6.0
PKG_RELEASE:=1
PKG_USE_MIPS16:=0
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-gpl.tgz
PKG_SOURCE_URL:=https://tls.mbed.org/download/
PKG_HASH:=312f020006f0d8e9ede3ed8e73d907a629baf6475229703941769372ab0adee2
PKG_HASH:=a99959d7360def22f9108d2d487c9de384fe76c349697176b1f22370080d5810
PKG_BUILD_PARALLEL:=1
PKG_LICENSE:=GPL-2.0+

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@ -1,6 +1,6 @@
--- a/include/mbedtls/config.h
+++ b/include/mbedtls/config.h
@@ -191,7 +191,7 @@
@@ -220,7 +220,7 @@
*
* Uncomment to get errors on using deprecated functions.
*/
@ -9,7 +9,7 @@
/* \} name SECTION: System support */
@@ -504,17 +504,17 @@
@@ -539,17 +539,17 @@
*
* Comment macros to disable the curve and functions for it
*/
@ -35,7 +35,7 @@
#define MBEDTLS_ECP_DP_CURVE25519_ENABLED
/**
@@ -539,8 +539,8 @@
@@ -574,8 +574,8 @@
* Requires: MBEDTLS_HMAC_DRBG_C
*
* Comment this macro to disable deterministic ECDSA.
@ -45,7 +45,7 @@
/**
* \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
@@ -586,7 +586,7 @@
@@ -621,7 +621,7 @@
* MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
* MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
*/
@ -54,7 +54,7 @@
/**
* \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
@@ -605,8 +605,8 @@
@@ -640,8 +640,8 @@
* MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
* MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
* MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
@ -64,7 +64,7 @@
/**
* \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
@@ -631,7 +631,7 @@
@@ -666,7 +666,7 @@
* MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
* MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
*/
@ -73,7 +73,7 @@
/**
* \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
@@ -758,7 +758,7 @@
@@ -793,7 +793,7 @@
* MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
* MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
*/
@ -82,7 +82,7 @@
/**
* \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
@@ -782,7 +782,7 @@
@@ -817,7 +817,7 @@
* MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
* MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
*/
@ -91,7 +91,7 @@
/**
* \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
@@ -886,7 +886,7 @@
@@ -921,7 +921,7 @@
* This option is only useful if both MBEDTLS_SHA256_C and
* MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used.
*/
@ -100,7 +100,7 @@
/**
* \def MBEDTLS_ENTROPY_NV_SEED
@@ -980,14 +980,14 @@
@@ -1015,14 +1015,14 @@
* Uncomment this macro to disable the use of CRT in RSA.
*
*/
@ -117,7 +117,7 @@
/**
* \def MBEDTLS_SHA256_SMALLER
@@ -1003,7 +1003,7 @@
@@ -1038,7 +1038,7 @@
*
* Uncomment to enable the smaller implementation of SHA256.
*/
@ -126,7 +126,7 @@
/**
* \def MBEDTLS_SSL_ALL_ALERT_MESSAGES
@@ -1122,8 +1122,8 @@
@@ -1157,8 +1157,8 @@
* misuse/misunderstand.
*
* Comment this to disable support for renegotiation.
@ -136,7 +136,7 @@
/**
* \def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
@@ -1297,8 +1297,8 @@
@@ -1332,8 +1332,8 @@
* callbacks are provided by MBEDTLS_SSL_TICKET_C.
*
* Comment this macro to disable support for SSL session tickets
@ -146,7 +146,7 @@
/**
* \def MBEDTLS_SSL_EXPORT_KEYS
@@ -1328,7 +1328,7 @@
@@ -1363,7 +1363,7 @@
*
* Comment this macro to disable support for truncated HMAC in SSL
*/
@ -155,7 +155,7 @@
/**
* \def MBEDTLS_THREADING_ALT
@@ -1362,8 +1362,8 @@
@@ -1397,8 +1397,8 @@
* Requires: MBEDTLS_VERSION_C
*
* Comment this to disable run-time checking and save ROM space
@ -165,7 +165,7 @@
/**
* \def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
@@ -1684,7 +1684,7 @@
@@ -1719,7 +1719,7 @@
* MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
* MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
*/
@ -174,7 +174,7 @@
/**
* \def MBEDTLS_CCM_C
@@ -1698,7 +1698,7 @@
@@ -1733,7 +1733,7 @@
* This module enables the AES-CCM ciphersuites, if other requisites are
* enabled as well.
*/
@ -183,7 +183,7 @@
/**
* \def MBEDTLS_CERTS_C
@@ -1710,7 +1710,7 @@
@@ -1745,7 +1745,7 @@
*
* This module is used for testing (ssl_client/server).
*/
@ -192,7 +192,7 @@
/**
* \def MBEDTLS_CIPHER_C
@@ -1763,7 +1763,7 @@
@@ -1798,7 +1798,7 @@
*
* This module provides debugging functions.
*/
@ -201,7 +201,7 @@
/**
* \def MBEDTLS_DES_C
@@ -1788,8 +1788,8 @@
@@ -1823,8 +1823,8 @@
* MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
*
* PEM_PARSE uses DES/3DES for decrypting encrypted keys.
@ -211,7 +211,7 @@
/**
* \def MBEDTLS_DHM_C
@@ -1943,8 +1943,8 @@
@@ -1978,8 +1978,8 @@
* Requires: MBEDTLS_MD_C
*
* Uncomment to enable the HMAC_DRBG random number geerator.
@ -221,7 +221,7 @@
/**
* \def MBEDTLS_MD_C
@@ -2221,7 +2221,7 @@
@@ -2256,7 +2256,7 @@
* Caller: library/md.c
*
*/
@ -230,7 +230,7 @@
/**
* \def MBEDTLS_RSA_C
@@ -2299,8 +2299,8 @@
@@ -2334,8 +2334,8 @@
* Caller:
*
* Requires: MBEDTLS_SSL_CACHE_C
@ -240,7 +240,7 @@
/**
* \def MBEDTLS_SSL_COOKIE_C
@@ -2321,8 +2321,8 @@
@@ -2356,8 +2356,8 @@
* Caller:
*
* Requires: MBEDTLS_CIPHER_C
@ -250,7 +250,7 @@
/**
* \def MBEDTLS_SSL_CLI_C
@@ -2421,8 +2421,8 @@
@@ -2456,8 +2456,8 @@
* Module: library/version.c
*
* This module provides run-time version information.
@ -260,7 +260,7 @@
/**
* \def MBEDTLS_X509_USE_C
@@ -2532,7 +2532,7 @@
@@ -2567,7 +2567,7 @@
* Module: library/xtea.c
* Caller:
*/

View File

@ -5,9 +5,9 @@ PKG_RELEASE=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(LEDE_GIT)/project/uclient.git
PKG_SOURCE_DATE:=2016-12-09
PKG_SOURCE_VERSION:=52d955fd802a4d990b7ff9116f02ff52aa63ffec
PKG_MIRROR_HASH:=b96f53ccaa62a229e818be836bb4fc85aa4a1ce257fd41fbdbf4e31a959c641f
PKG_SOURCE_DATE:=2017-09-06
PKG_SOURCE_VERSION:=24d6eded73dec427fc4a3a20cc73c94227f59c31
PKG_MIRROR_HASH:=e884ae0c859baa20a5c7f3d924022f8e1f57d28474dbe5fed1efb8fb97790dd0
CMAKE_INSTALL:=1
PKG_BUILD_DEPENDS:=ustream-ssl

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@ -68,5 +68,5 @@ Package/libustream-cyassl/install = $(Package/libustream/default/install)
Package/libustream-mbedtls/install = $(Package/libustream/default/install)
$(eval $(call BuildPackage,libustream-mbedtls))
#$(eval $(call BuildPackage,libustream-cyassl))
#$(eval $(call BuildPackage,libustream-openssl))
$(eval $(call BuildPackage,libustream-cyassl))
$(eval $(call BuildPackage,libustream-openssl))

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@ -8,13 +8,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=odhcp6c
PKG_RELEASE:=3
PKG_RELEASE:=4
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(LEDE_GIT)/project/odhcp6c.git
PKG_SOURCE_DATE:=2017-09-02
PKG_SOURCE_DATE:=2017-09-05
PKG_SOURCE_VERSION:=51733a6d3bfe0fb9e8c53aea22231e5b8a1f64c3
PKG_MIRROR_HASH:=7ab8d3755c588b493792110d871c682cdd8e944ae21db64177321c464c104fb3
PKG_MIRROR_HASH:=fdccfb9a6cb00d6dbf1a3160bd36622ee8e188a9d58bcd282c71a9368972e184
PKG_MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>
PKG_LICENSE:=GPL-2.0

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@ -81,6 +81,23 @@ setup_interface () {
# RFC 7278
if [ "$mask" -eq 64 -a -z "$PREFIXES" -a -n "$EXTENDPREFIX" ]; then
proto_add_ipv6_prefix "$addr/$mask,$preferred,$valid"
local raroutes=""
for route in $RA_ROUTES; do
local prefix="${route%%/*}"
local entry="${route#*/}"
local pmask="${entry%%,*}"
entry="${entry#*,}"
local gw="${entry%%,*}"
[ -z "$gw" -a "$mask" = "$pmask" ] && {
case "$addr" in
"${prefix%*::}"*) continue;;
esac
}
raroutes="$raroutes $route"
done
RA_ROUTES="$raroutes"
fi
done

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@ -1,116 +0,0 @@
#
# Copyright (C) 2006-2014 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=emailrelay
PKG_VERSION:=1.9
PKG_RELEASE:=2
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-src.tar.gz
PKG_SOURCE_URL:=@SF/emailrelay/$(PKG_VERSION)
PKG_MD5SUM:=0892fbf993407c6b5a16f96e23299b62
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
include $(INCLUDE_DIR)/uclibc++.mk
include $(INCLUDE_DIR)/package.mk
define Package/emailrelay/Default
SECTION:=net
SUBMENU:=Web Servers/Proxies
CATEGORY:=Network
DEPENDS:=$(CXX_DEPENDS)
TITLE:=A simple SMTP proxy and MTA
URL:=http://emailrelay.sourceforge.net/
MAINTAINER := Federico Di Marco <fededim@gmail.com>
endef
define Package/emailrelay
$(call Package/emailrelay/Default)
TITLE+= (with OpenSSL support)
DEPENDS+=+libopenssl
VARIANT:=ssl
endef
define Package/emailrelay-nossl
$(call Package/emailrelay/Default)
TITLE+= (no SSL support)
VARIANT:=nossl
endef
define Package/emailrelay/Default/description
Emailrelay is a simple SMTP proxy and store-and-forward message transfer agent (MTA).
When running as a proxy all e-mail messages can be passed through
a user-defined program, such as a spam filter, which can drop,
re-address or edit messages as they pass through. When running
as a store-and-forward MTA incoming messages are stored in a
local spool directory, and then forwarded to the next SMTP
server on request.
endef
define Package/emailrelay/description
$(call Package/emailrelay/Default/description)
This package is built with OpenSSL support (SSMTP is supported).
endef
define Package/emailrelay-nossl/description
$(call Package/emailrelay/Default/description)
This package is built without SSL support (no SSMTP)
endef
define Package/emailrelay/conffiles
/etc/emailrelay.auth
endef
define Package/emailrelay-nossl/conffiles
/etc/emailrelay.auth
endef
CONFIGURE_ARGS += \
--with-pam=no
CONFIGURE_VARS += \
CXXFLAGS="$$$$CXXFLAGS -fno-rtti"
ifeq ($(BUILD_VARIANT),ssl)
CONFIGURE_ARGS += \
--with-openssl
endif
ifeq ($(BUILD_VARIANT),nossl)
CONFIGURE_ARGS += \
--with-openssl=no
endif
define Package/emailrelay/install
$(INSTALL_DIR) $(1)/usr/bin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/main/emailrelay $(1)/usr/bin/
$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/main/emailrelay-filter-copy $(1)/usr/bin/
$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/main/emailrelay-passwd $(1)/usr/bin/
$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/main/emailrelay-poke $(1)/usr/bin/
$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/main/emailrelay-submit $(1)/usr/bin/
$(INSTALL_DIR) $(1)/etc
$(INSTALL_DATA) files/$(PKG_NAME).auth $(1)/etc/
$(INSTALL_DIR) $(1)/etc/init.d
$(INSTALL_BIN) files/$(PKG_NAME).init $(1)/etc/init.d/$(PKG_NAME)
endef
Package/emailrelay-nossl/install = $(Package/emailrelay/install)
$(eval $(call BuildPackage,emailrelay))
$(eval $(call BuildPackage,emailrelay-nossl))

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@ -1,16 +0,0 @@
#
# emailrelay secrets file
#
#see http://emailrelay.sourceforge.net/reference.html for reference
#Mostly used options:
#
#NONE server specifies ip address range allowed to connect to emailrelay SMTP server
#LOGIN client specifies the credentials to be used when forwarding emails to another SMTP server
#LOGIN server specifies the credentials to be needed to authenticate with the emailrelay SMTP server
#Examples:
#
#NONE server 192.168.1.* keyword
#LOGIN client smtpuser@smtpserver smtppassword
#LOGIN server user1 secret

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@ -1,15 +0,0 @@
#!/bin/sh /etc/rc.common
#see http://emailrelay.sourceforge.net/reference.html for command line reference
START=90
start() {
logger -t 'emailrelay' "Starting emailrelay service."
service_start /usr/bin/emailrelay --as-server --poll 60 --forward-to smtpserver:smtpport --spool-dir /tmp --client-tls --client-auth /etc/emailrelay.auth --server-auth /etc/emailrelay.auth --log
}
stop() {
logger -t 'emailrelay' "Stopping emailrelay service."
service_stop /usr/bin/emailrelay
}

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@ -1,35 +0,0 @@
diff -Nurp emailrelay-1.9/src/glib/gstr.cpp emailrelay-1.9-new/src/glib/gstr.cpp
--- emailrelay-1.9/src/glib/gstr.cpp 2013-12-07 23:55:43.000000000 +0100
+++ emailrelay-1.9-new/src/glib/gstr.cpp 2016-05-21 03:50:36.178681099 +0200
@@ -546,7 +546,7 @@ void G::Str::readLineFrom( std::istream
if( pre_erase )
line.erase() ;
-
+/*
// this is a special speed optimisation for a two-character terminator with a one-character initial string ;-)
if( eol.length() == 2U && eol[0] != eol[1] && line.length() == 1U )
{
@@ -577,9 +577,9 @@ void G::Str::readLineFrom( std::istream
}
}
else
- {
+ { */
readLineFromImp( stream , eol , line ) ;
- }
+// }
}
void G::Str::readLineFromImp( std::istream & stream , const std::string & eol , std::string & line )
diff -Nurp emailrelay-1.9/src/gsmtp/gserverprotocol.cpp emailrelay-1.9-new/src/gsmtp/gserverprotocol.cpp
--- emailrelay-1.9/src/gsmtp/gserverprotocol.cpp 2013-12-07 23:55:46.000000000 +0100
+++ emailrelay-1.9-new/src/gsmtp/gserverprotocol.cpp 2016-05-21 17:52:18.682367416 +0200
@@ -608,7 +608,6 @@ std::string GSmtp::ServerProtocol::comma
std::string GSmtp::ServerProtocol::commandLine( const std::string & line_in ) const
{
std::string line( line_in ) ;
- G::Str::trimLeft( line , " \t" ) ;
return line ;
}

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@ -1,16 +0,0 @@
--- a/src/gssl/gssl_openssl.cpp 2016-08-12 16:14:04.122314793 +0200
+++ b/src/gssl/gssl_openssl.cpp 2016-08-12 16:17:11.969303185 +0200
@@ -290,12 +290,7 @@ namespace
GSsl::Context::Context( const std::string & pem_file , unsigned int flags )
{
- if( (flags&3U) == 2U )
- m_ssl_ctx = SSL_CTX_new(SSLv23_method()) ;
- else if( (flags&3U) == 3U )
- m_ssl_ctx = SSL_CTX_new(SSLv3_method()) ;
- else
- m_ssl_ctx = SSL_CTX_new(TLSv1_method()) ;
+ m_ssl_ctx = SSL_CTX_new(SSLv23_method()) ;
if( m_ssl_ctx == NULL )
throw Error( "SSL_CTX_new" , ERR_get_error() ) ;

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@ -152,9 +152,6 @@ hostapd_common_add_bss_config() {
config_add_string auth_secret
config_add_int 'auth_port:port' 'port:port'
config_add_int eap_server
config_add_string ca_cert server_cert private_key eap_user_file
config_add_string acct_server
config_add_string acct_secret
config_add_int acct_port
@ -293,47 +290,24 @@ hostapd_set_bss_options() {
json_get_vars \
auth_server auth_secret auth_port \
dae_client dae_secret dae_port \
ownip eap_server \
ownip \
eap_reauth_period
# radius can provide VLAN ID for clients
vlan_possible=1
set_default eap_server 1
append bss_conf "eap_server=$eap_server" "$N"
if [ "$eap_server" = "1" ]; then
json_get_vars \
server_cert private_key \
eap_user_file ca_cert
# legacy compatibility
[ -n "$auth_server" ] || json_get_var auth_server server
[ -n "$auth_port" ] || json_get_var auth_port port
[ -n "$auth_secret" ] || json_get_var auth_secret key
set_default private_key /etc/ssl/private/N3TW0RK-SAT02-key.pem
set_default server_cert /etc/ssl/private/N3TW0RK-SAT02-cert.pem
set_default eap_user_file /etc/config/eap_user_file
set_default auth_port 1812
set_default dae_port 3799
append bss_conf "ca_cert=$ca_cert" "$N"
append bss_conf "server_cert=$server_cert" "$N"
append bss_conf "private_key=$private_key" "$N"
append bss_conf "eap_user_file=$eap_user_file" "$N"
else
# legacy compatibility
[ -n "$auth_server" ] || json_get_var auth_server server
[ -n "$auth_port" ] || json_get_var auth_port port
[ -n "$auth_secret" ] || json_get_var auth_secret key
set_default auth_port 1812
set_default dae_port 3799
append bss_conf "auth_server_addr=$auth_server" "$N"
append bss_conf "auth_server_port=$auth_port" "$N"
append bss_conf "auth_server_shared_secret=$auth_secret" "$N"
[ -n "$acct_server" ] && {
append bss_conf "acct_server_addr=$acct_server" "$N"
append bss_conf "acct_server_port=$acct_port" "$N"
[ -n "$acct_secret" ] && \
append bss_conf "acct_server_shared_secret=$acct_secret" "$N"
}
fi
append bss_conf "auth_server_addr=$auth_server" "$N"
append bss_conf "auth_server_port=$auth_port" "$N"
append bss_conf "auth_server_shared_secret=$auth_secret" "$N"
[ -n "$eap_reauth_period" ] && append bss_conf "eap_reauth_period=$eap_reauth_period" "$N"
@ -398,7 +372,7 @@ hostapd_set_bss_options() {
[ -n "$network_bridge" ] && append bss_conf "bridge=$network_bridge" "$N"
[ -n "$iapp_interface" ] && {
local ifname
network_get_device ifname "$iapp_interface" || ifname = "$iapp_interface"
network_get_device ifname "$iapp_interface" || ifname="$iapp_interface"
append bss_conf "iapp_interface=$ifname" "$N"
}

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@ -8,12 +8,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=lldpd
PKG_VERSION:=0.9.7
PKG_VERSION:=0.9.8
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=http://media.luffy.cx/files/lldpd
PKG_HASH:=b9360355c30a3c06fd5c0a6e658f2ad8bf77037d5a17c6fcabf20e62882e0db8
PKG_HASH:=9ee494e91bc33938575b2c09b26188c486ef8eac6e2155d250c189cc4e988c4f
PKG_MAINTAINER:=Stijn Tintel <stijn@linux-ipv6.be>
PKG_LICENSE:=ISC

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@ -1,48 +0,0 @@
#
# Copyright (C) 2015 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=upnpbridge
PKG_RELEASE=1
PKG_MAINTAINER:=
PKG_LICENSE:=GPL-2.0
include $(INCLUDE_DIR)/package.mk
define Package/upnpbridge
SECTION:=net
CATEGORY:=Network
TITLE:=OpenWrt UPNP Multicast Bridge
DEPENDS:=+USE_GLIBC:librt
endef
PKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME)
define Build/Prepare
mkdir -p $(PKG_BUILD_DIR)
$(CP) ./src/* $(PKG_BUILD_DIR)/
endef
define Build/Configure
endef
define Build/Compile
$(MAKE) -C $(PKG_BUILD_DIR) \
CC="$(TARGET_CC)" \
CFLAGS="$(TARGET_CFLAGS) -Wall" \
LDFLAGS="$(TARGET_LDFLAGS)"
endef
define Package/upnpbridge/install
$(INSTALL_DIR) $(1)/usr/sbin $(1)/etc/init.d
$(INSTALL_BIN) $(PKG_BUILD_DIR)/upnpbridge $(1)/usr/sbin/
$(INSTALL_BIN) ./files/upnpbridge.init $(1)/etc/init.d/upnpbridge
endef
$(eval $(call BuildPackage,upnpbridge))

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@ -1,28 +0,0 @@
#!/bin/sh /etc/rc.common
START=99
STOP=99
UPNPBRIDGE_BIN="/usr/sbin/upnpbridge"
SERVICE_DAEMONIZE=1
SERVICE_WRITE_PID=1
# UPnPbridge bridges SSDP datagrams between interfaces.
# At least 2 interfaces must be specified on the command line.
#
# Usage: ./upnpbridge-orig eth0 br-lan [...]
INTERFACES="eth0 br-lan"
start() {
service_start $UPNPBRIDGE_BIN $INTERFACES
}
stop() {
service_stop $UPNPBRIDGE_BIN
}
reload() {
service_reload $UPNPBRIDGE_BIN
}

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@ -1 +0,0 @@
upnpbridge: upnpbridge.c

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@ -1,345 +0,0 @@
/******
*
* U P N P B R I D G E . C
*
******/
#include <stdio.h>
#include <netinet/in.h>
#include <sys/socket.h>
#include <sys/types.h>
#include <errno.h>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/param.h>
#include <net/if.h>
#include <malloc.h>
#include <stdlib.h>
#include <netinet/in_systm.h>
#include <netinet/in.h>
#include <netinet/ip.h>
#include <netinet/udp.h>
#include <stdio.h>
#include <ctype.h>
struct psd_udp {
struct in_addr src;
struct in_addr dst;
unsigned char pad;
unsigned char proto;
unsigned short udp_len;
struct udphdr udp;
} __attribute__((__packed__));
struct in_addr ssdpaddr;
#define SSDPADDR "239.255.255.250"
#define SSDPPORT 1900
//#define debugprint 1
#define debugprint 0
#define dbgprintf if (debugprint) fprintf
#define ERRPRINT(rv) if (rv < 0) dbgprintf(stderr, "Errno: %d, %s\n", errno, strerror(errno))
static void print_hex_dump_bytes(const char *pre, const void *buf,
size_t len)
{
char line[58];
char str[17] = { 0 };
const unsigned char *tmp = (const void *) buf;
char *pbuf = line;
size_t i;
for (i = 0; i < len; i++) {
if (i % 16 == 0) {
if (pbuf != line) {
printf("%s%s: %s\n", pre ? pre : "", line, str);
pbuf = line;
}
pbuf += sprintf(pbuf, "0x%04lx: ", (unsigned long)i);
}
pbuf += sprintf(pbuf, "%.2x ", tmp[i]);
str[i % 16] = (isprint(tmp[i]) && isascii(tmp[i])) ? tmp[i] : '.';
}
if (pbuf != line) {
if ((i % 16)) {
str[i % 16] = '\0';
for (i = 16 - (i % 16); i != 0; i--)
pbuf += sprintf(pbuf, " ");
}
printf("%s%s: %s\n", pre, line, str);
}
}
typedef struct ll2WaySocket_t {
struct ll2WaySocket_t *next;
int rxs, txs;
char *rxn, *txn;
} ll2WaySocket_t;
ll2WaySocket_t *lls = NULL;
unsigned long
get_ip_by_spec(char *spec)
{
int fd;
int badlen;
struct ifreq ifr;
struct in_addr addr;
/* If the string badlen chars long, it's not a valid */
/* IP address or interface name. An IPv4 address is */
/* at max 15 characters long. */
badlen = MAX(IF_NAMESIZE, 16);
if (strnlen(spec, badlen) < badlen) {
fd = socket(AF_INET, SOCK_DGRAM, IPPROTO_IP);
if (fd < 0)
return 0L; /* internal error */
memset(&ifr, 0, sizeof(struct ifreq));
strcpy(ifr.ifr_name, spec);
ifr.ifr_addr.sa_family = AF_INET;
if (ioctl(fd, SIOCGIFADDR, &ifr) >= 0) {
close(fd);
return (((struct sockaddr_in *) &ifr.ifr_addr)->sin_addr.s_addr);
}
close(fd);
}
return 0L;
}
void initialise(int argc, char *argv[])
{
int retval;
int argn;
struct ll2WaySocket_t **cplls = &lls;
ssdpaddr.s_addr = inet_addr(SSDPADDR);
if (argc < 3)
{
printf("UPnPbridge bridges SSDP datagrams between interfaces.\nAt least 2 interfaces must be specified on the command line.\n\nUsage: %s if1 if2 [...]\n", argv[0]);
exit(1);
}
else for (argn=1; argn<argc; argn++)
{
struct in_addr itfaddr;
dbgprintf(stderr, "\nProcessing argv[%d]=%s\n", argn, argv[argn]);
if (0L == (itfaddr.s_addr = get_ip_by_spec(argv[argn])))
{
fprintf(stderr, "%s: Unknown interface name (%s)\n", argv[0], argv[argn]);
exit(1);
}
dbgprintf(stderr, "Interface address 0x%lx; ", itfaddr.s_addr);
if (NULL == (*cplls = malloc(sizeof(ll2WaySocket_t))))
{
fprintf(stderr, "%s: Memory allocation error\n", argv[0]);
exit(1);
}
memset(*cplls, 0, sizeof(ll2WaySocket_t));
(**cplls).rxs = socket(AF_INET, SOCK_RAW, IPPROTO_UDP);
(**cplls).txs = socket(AF_INET, SOCK_RAW, IPPROTO_RAW);
dbgprintf(stderr, "Created rxs(%d) and txs(%d); ", (**cplls).rxs, (**cplls).txs);
(**cplls).rxn = (**cplls).txn = argv[argn];
{
u_int hi = 1;
retval = setsockopt((**cplls).rxs, IPPROTO_IP, IP_HDRINCL, &hi, sizeof(hi));
dbgprintf(stderr, "setsockopt(%d, IP, HDRINCL, [%d], %d)=%d; ", (**cplls).rxs, hi, sizeof(hi), retval);
ERRPRINT(retval);
retval = setsockopt((**cplls).txs, IPPROTO_IP, IP_HDRINCL, &hi, sizeof(hi));
dbgprintf(stderr, "setsockopt(%d, IP, HDRINCL, [%d], %d)=%d; ", (**cplls).txs, hi, sizeof(hi), retval);
ERRPRINT(retval);
}
{
u_int on = 1;
retval = setsockopt((**cplls).rxs, SOL_SOCKET, SO_REUSEADDR, &on, sizeof(on));
dbgprintf(stderr, "setsockopt(%d, SOCK, REUS, [%d], %d)=%d; ", (**cplls).rxs, on, sizeof(on), retval);
ERRPRINT(retval);
retval = setsockopt((**cplls).txs, SOL_SOCKET, SO_REUSEADDR, &on, sizeof(on));
dbgprintf(stderr, "setsockopt(%d, SOCK, REUS, [%d], %d)=%d; ", (**cplls).txs, on, sizeof(on), retval);
ERRPRINT(retval);
}
{
struct sockaddr_in sa;
sa.sin_family = AF_INET;
sa.sin_addr.s_addr = ssdpaddr.s_addr;
sa.sin_port = htons(SSDPPORT);
retval = bind((**cplls).rxs, (struct sockaddr *)&sa, sizeof(sa));
dbgprintf(stderr, "bind(%d, {%d, 0x%lx, %d}, %d)=%d; ", (**cplls).rxs, AF_INET, sa.sin_addr.s_addr, SSDPPORT, sizeof(sa), retval);
ERRPRINT(retval);
retval = bind((**cplls).txs, (struct sockaddr *)&sa, sizeof(sa));
dbgprintf(stderr, "bind(%d, {%d, 0x%lx, %d}, %d)=%d; ", (**cplls).txs, AF_INET, sa.sin_addr.s_addr, SSDPPORT, sizeof(sa), retval);
ERRPRINT(retval);
}
{
u_int loop = 0;
retval = setsockopt((**cplls).txs, IPPROTO_IP, IP_MULTICAST_LOOP, &loop, sizeof(loop));
dbgprintf(stderr, "setsockopt(%d, IP, MCAST_LOOP, [%d], %d)=%d; ", (**cplls).txs, loop, sizeof(loop), retval);
ERRPRINT(retval);
}
{
u_int ttl = 4;
retval = setsockopt((**cplls).txs, SOL_IP, IP_MULTICAST_TTL, &ttl, sizeof(ttl));
dbgprintf(stderr, "setsockopt(%d, IP, TTL, [%d], %d)=%d; ", (**cplls).txs, ttl, sizeof(ttl), retval);
ERRPRINT(retval);
}
{
retval = setsockopt((**cplls).txs, SOL_IP, IP_MULTICAST_IF, &itfaddr, sizeof(itfaddr));
dbgprintf(stderr, "setsockopt(%d, IP, MCAST_IF, 0x%lx, %d)=%d; ", (**cplls).txs, itfaddr.s_addr, sizeof(itfaddr), retval);
ERRPRINT(retval);
}
{
struct ip_mreqn membership;
membership.imr_multiaddr.s_addr = ssdpaddr.s_addr;
membership.imr_address = itfaddr;
dbgprintf(stderr, "rxn=%s; ", (**cplls).rxn);
membership.imr_ifindex = if_nametoindex((**cplls).rxn);
dbgprintf(stderr, "imr_ifindex=%d; ", membership.imr_ifindex);
retval = setsockopt((**cplls).rxs, SOL_IP, IP_ADD_MEMBERSHIP, &membership, sizeof(membership));
dbgprintf(stderr, "setsockopt(%d, IP, ADD_MEM, {{0x%lx, 0x%lx, %d}, %d)=%d; ", (**cplls).rxs, membership.imr_multiaddr.s_addr, membership.imr_address.s_addr, membership.imr_ifindex, sizeof(membership), retval);
ERRPRINT(retval);
retval = setsockopt((**cplls).rxs, SOL_SOCKET, SO_BINDTODEVICE, (**cplls).rxn, 1+strlen((**cplls).rxn));
dbgprintf(stderr, "setsockopt(%d, SOCK, BIND2DEV, %s, %d)=%d; ", (**cplls).rxs, (**cplls).rxn, 1+strlen((**cplls).rxn), retval);
ERRPRINT(retval);
}
cplls = &((**cplls).next);
dbgprintf(stderr, "\n\n");
}
}
unsigned short in_cksum(unsigned short *addr, int len)
{
int nleft = len;
int sum = 0;
unsigned short *w = addr;
unsigned short answer = 0;
while (nleft > 1) {
sum += *w++;
nleft -= 2;
}
if (nleft == 1) {
*(unsigned char *) (&answer) = *(unsigned char *) w;
sum += answer;
}
sum = (sum >> 16) + (sum & 0xFFFF);
sum += (sum >> 16);
answer = ~sum;
return (answer);
}
unsigned short in_cksum_udp(int src, int dst, unsigned short *addr, int len)
{
struct psd_udp buf;
memset(&buf, 0, sizeof(buf));
buf.src.s_addr = src;
buf.dst.s_addr = dst;
buf.pad = 0;
buf.proto = IPPROTO_UDP;
buf.udp_len = htons(len);
memcpy(&(buf.udp), addr, len);
return in_cksum((unsigned short *)&buf, 12 + len);
}
void doTheBusiness()
{
struct sockaddr_in sa;
ll2WaySocket_t **cplls, **iplls, **oplls;
sa.sin_family = AF_INET;
sa.sin_addr.s_addr = ssdpaddr.s_addr;
sa.sin_port = htons(SSDPPORT);
while (1)
{
fd_set rfds;
struct timeval tv;
int retval, maxs;
FD_ZERO(&rfds);
for (cplls = &lls, maxs = 0; NULL != *cplls; cplls = &((**cplls).next))
{
FD_SET((**cplls).rxs, &rfds);
if ((**cplls).rxs > maxs) maxs = (**cplls).rxs;
}
tv.tv_sec = 1000; tv.tv_usec=0;
retval = select(1+maxs, &rfds, NULL, NULL, &tv);
if (retval)
{
for (iplls = &lls; NULL != *iplls; iplls = &((**iplls).next))
{
if (FD_ISSET((**iplls).rxs, &rfds))
{
u_char buf[2048];
struct sockaddr from;
socklen_t fromlen=0;
int recvlen;
memset(buf, 0, sizeof(buf));
recvlen = recvfrom((**iplls).rxs, buf, sizeof(buf)-1, 0, &from, &fromlen);
if (recvlen > 0)
for (oplls = &lls; NULL != *oplls; oplls = &((**oplls).next))
if ((**iplls).rxs != (**oplls).rxs) {
retval = sendto((**oplls).txs, buf, recvlen, 0, &sa, sizeof(sa));
if (retval != recvlen) dbgprintf(stderr, "sendto %s error %d\n", (**oplls).txn, retval);
ERRPRINT(retval);
}
}
}
}
}
}
void deinitialise()
{
}
int main(int argc, char *argv[])
{
initialise(argc, argv);
doTheBusiness();
deinitialise();
exit(0);
}

View File

@ -1,27 +0,0 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=linkwatch
PKG_VERSION:=2016-02-17
PKG_RELEASE=1
include $(INCLUDE_DIR)/package.mk
define Package/linkwatch
SECTION:=net
CATEGORY:=Network
TITLE:=Manual link dhcp link updater for bridged wan
endef
define Build/Compile
true
endef
define Package/linkwatch/install
$(INSTALL_DIR) $(1)/usr/sbin/
$(INSTALL_BIN) ./files/linkwatch $(1)/usr/sbin
$(INSTALL_DIR) $(1)/etc/init.d
$(INSTALL_BIN) ./files/linkwatch.init $(1)/etc/init.d/linkwatch
endef
$(eval $(call BuildPackage,linkwatch))

View File

@ -1,125 +0,0 @@
#!/bin/sh
. /lib/functions.sh
. /lib/functions/network.sh
. /usr/share/libubox/jshn.sh
[ -x /sbin/swconfig -a -r /etc/board.json ] || exit 1
INTERVAL=2 # Sleep interval in Seconds
PREVSTATE=-1 # -1 = Don't Know, 0 = Down, 1 = Up
WAN=
DEV=
PHY=
SWITCH=
WANPORT=
find_wan_port() {
local key keys port ports device role num device found
json_get_keys keys switch
json_select switch
for key in $keys; do
json_select $key
if json_is_a ports array; then
json_get_keys ports ports
json_select ports
found=0
for port in $ports; do
json_select "$port"
json_get_vars num role device
json_select ..
[ "$device" = "$PHY" ] && found=1
[ "$found" = "1" -a "$role" = "$WAN" ] && {
WANPORT="$num"
SWITCH="$key"
json_select ..
json_select ..
json_select ..
return
}
done
json_select ..
fi
json_select ..
done
json_select ..
}
find_dev() {
local key keys ifname
json_get_keys keys network
json_select network
for key in $keys; do
[ "$key" = "$WAN" ] && {
json_select $key
json_get_vars ifname
DEV="$ifname"
json_select ..
break
}
done
json_select ..
}
setup() {
json_init
json_load "$(cat /tmp/board.json)"
[ -z "$WAN" ] && network_find_wan WAN
[ -z "$WAN" ] || {
[ -z "$DEV" ] && find_dev
[ -z "$PHY" ] && PHY=${DEV%.*}
[ -z "$DEV" -o -z "$PHY" ] || find_wan_port
}
}
watch() {
logger "monitor connections on $WAN($DEV)"
while $(/bin/ubus call network.interface.$WAN status &> /dev/null); do
link=$(swconfig dev "$SWITCH" port "$WANPORT" get link)
case "$link" in
*"link:up"*)
[ "$PREVSTATE" = "1" ] || {
logger "Detected Interface UP"
[ "$PREVSTATE" = "0" ] && {
ip link set $DEV up
ubus call network.interface.$WAN renew
}
}
PREVSTATE=1
;;
*"link:down"*)
[ "$PREVSTATE" = "0" ] || {
logger "Detected Interface DOWN"
[ "$PREVSTATE" = "1" ] && {
ip link set $DEV down
}
}
PREVSTATE=0
;;
esac
sleep $INTERVAL
done
}
logger "Started Linkwatch"
while (/bin/true); do
setup
[ -z "$WAN" -o -z "$DEV" -o -z "$SWITCH" -o -z "$WANPORT" ] || watch
echo wait
sleep 10
done

View File

@ -1,20 +0,0 @@
#!/bin/sh /etc/rc.common
START=99
STOP=99
LINKWATCH_BIN="/usr/sbin/linkwatch"
SERVICE_DAEMONIZE=1
SERVICE_WRITE_PID=1
start() {
service_start $LINKWATCH_BIN
}
stop() {
service_stop $LINKWATCH_BIN
}
reload() {
service_reload $LINKWATCH_BIN
}

View File

@ -8,13 +8,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=tcpdump
PKG_VERSION:=4.9.1
PKG_VERSION:=4.9.2
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=http://www.us.tcpdump.org/release/ \
http://www.tcpdump.org/release/
PKG_HASH:=f9448cf4deb2049acf713655c736342662e652ef40dbe0a8f6f8d5b9ce5bd8f3
PKG_HASH:=798b3536a29832ce0cbb07fafb1ce5097c95e308a6f592d14052e1ef1505fe79
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
PKG_BUILD_PARALLEL:=1

View File

@ -92,7 +92,7 @@
LIBOBJS = @LIBOBJS@
--- a/addrtoname.c
+++ b/addrtoname.c
@@ -566,8 +566,10 @@ linkaddr_string(netdissect_options *ndo,
@@ -578,8 +578,10 @@ linkaddr_string(netdissect_options *ndo,
if (type == LINKADDR_ETHER && len == ETHER_ADDR_LEN)
return (etheraddr_string(ndo, ep));
@ -102,8 +102,8 @@
+#endif
tp = lookup_bytestring(ndo, ep, len);
if (tp->e_name)
@@ -1202,6 +1204,7 @@ init_addrtoname(netdissect_options *ndo,
if (tp->bs_name)
@@ -1214,6 +1216,7 @@ init_addrtoname(netdissect_options *ndo,
init_ipxsaparray(ndo);
}
@ -111,7 +111,7 @@
const char *
dnaddr_string(netdissect_options *ndo, u_short dnaddr)
{
@@ -1221,6 +1224,7 @@ dnaddr_string(netdissect_options *ndo, u
@@ -1233,6 +1236,7 @@ dnaddr_string(netdissect_options *ndo, u
return(tp->name);
}
@ -224,7 +224,7 @@
return (1);
@@ -368,6 +369,7 @@ ethertype_print(netdissect_options *ndo,
}
isoclns_print(ndo, p + 1, length - 1, caplen - 1);
isoclns_print(ndo, p + 1, length - 1);
return(1);
+#endif
@ -312,7 +312,7 @@
break;
--- a/print-ip6.c
+++ b/print-ip6.c
@@ -303,6 +303,7 @@ ip6_print(netdissect_options *ndo, const
@@ -305,6 +305,7 @@ ip6_print(netdissect_options *ndo, const
return;
nh = *cp;
break;
@ -320,13 +320,16 @@
case IPPROTO_FRAGMENT:
advance = frag6_print(ndo, cp, (const u_char *)ip6);
if (advance < 0 || ndo->ndo_snapend <= cp + advance)
@@ -324,16 +325,19 @@ ip6_print(netdissect_options *ndo, const
advance = mobility_print(ndo, cp, (const u_char *)ip6);
@@ -328,6 +329,7 @@ ip6_print(netdissect_options *ndo, const
return;
nh = *cp;
return;
+#endif
case IPPROTO_ROUTING:
ND_TCHECK(*cp);
advance = rt6_print(ndo, cp, (const u_char *)ip6);
@@ -335,12 +337,14 @@ ip6_print(netdissect_options *ndo, const
return;
nh = *cp;
break;
+#ifndef TCPDUMP_MINI
@ -340,15 +343,15 @@
case IPPROTO_TCP:
tcp_print(ndo, cp, len, (const u_char *)ip6, fragmented);
return;
@@ -343,6 +347,7 @@ ip6_print(netdissect_options *ndo, const
@@ -350,6 +354,7 @@ ip6_print(netdissect_options *ndo, const
case IPPROTO_ICMPV6:
icmp6_print(ndo, cp, len, (const u_char *)ip6, fragmented);
return;
+#ifndef TCPDUMP_MINI
case IPPROTO_AH:
advance = ah_print(ndo, cp);
nh = *cp;
@@ -371,6 +376,7 @@ ip6_print(netdissect_options *ndo, const
if (advance < 0)
@@ -382,6 +387,7 @@ ip6_print(netdissect_options *ndo, const
case IPPROTO_PIM:
pim_print(ndo, cp, len, (const u_char *)ip6);
return;
@ -356,7 +359,7 @@
case IPPROTO_OSPF:
ospf6_print(ndo, cp, len);
@@ -384,9 +390,11 @@ ip6_print(netdissect_options *ndo, const
@@ -395,9 +401,11 @@ ip6_print(netdissect_options *ndo, const
ip_print(ndo, cp, len);
return;
@ -370,7 +373,7 @@
gre_print(ndo, cp, len);
--- a/print-ip.c
+++ b/print-ip.c
@@ -329,6 +329,7 @@ ip_print_demux(netdissect_options *ndo,
@@ -344,6 +344,7 @@ ip_print_demux(netdissect_options *ndo,
again:
switch (ipds->nh) {
@ -378,7 +381,7 @@
case IPPROTO_AH:
if (!ND_TTEST(*ipds->cp)) {
ND_PRINT((ndo, "[|AH]"));
@@ -367,7 +368,9 @@ again:
@@ -382,7 +383,9 @@ again:
*/
break;
}
@ -388,7 +391,7 @@
case IPPROTO_SCTP:
sctp_print(ndo, ipds->cp, (const u_char *)ipds->ip, ipds->len);
break;
@@ -375,6 +378,7 @@ again:
@@ -390,6 +393,7 @@ again:
case IPPROTO_DCCP:
dccp_print(ndo, ipds->cp, (const u_char *)ipds->ip, ipds->len);
break;
@ -396,7 +399,7 @@
case IPPROTO_TCP:
/* pass on the MF bit plus the offset to detect fragments */
@@ -394,6 +398,7 @@ again:
@@ -409,6 +413,7 @@ again:
ipds->off & (IP_MF|IP_OFFMASK));
break;
@ -404,7 +407,7 @@
case IPPROTO_PIGP:
/*
* XXX - the current IANA protocol number assignments
@@ -414,14 +419,17 @@ again:
@@ -429,14 +434,17 @@ again:
case IPPROTO_EIGRP:
eigrp_print(ndo, ipds->cp, ipds->len);
break;
@ -422,7 +425,7 @@
case IPPROTO_OSPF:
ospf_print(ndo, ipds->cp, ipds->len, (const u_char *)ipds->ip);
@@ -454,6 +462,7 @@ again:
@@ -469,6 +477,7 @@ again:
gre_print(ndo, ipds->cp, ipds->len);
break;
@ -430,14 +433,14 @@
case IPPROTO_MOBILE:
mobile_print(ndo, ipds->cp, ipds->len);
break;
@@ -482,6 +491,7 @@ again:
@@ -497,6 +506,7 @@ again:
case IPPROTO_PGM:
pgm_print(ndo, ipds->cp, ipds->len, (const u_char *)ipds->ip);
break;
+#endif
default:
if (ndo->ndo_nflag==0 && (proto = getprotobynumber(ipds->nh)) != NULL)
if (ndo->ndo_nflag==0 && (p_name = netdb_protoname(ipds->nh)) != NULL)
--- a/print-llc.c
+++ b/print-llc.c
@@ -206,6 +206,7 @@ llc_print(netdissect_options *ndo, const
@ -472,21 +475,22 @@
#ifdef ENABLE_SMB
if (ssap == LLCSAP_NETBEUI && dsap == LLCSAP_NETBEUI
@@ -322,11 +326,13 @@ llc_print(netdissect_options *ndo, const
@@ -322,12 +326,13 @@ llc_print(netdissect_options *ndo, const
return (hdrlen);
}
#endif
+#ifndef TCPDUMP_MINI
if (ssap == LLCSAP_ISONS && dsap == LLCSAP_ISONS
&& control == LLC_UI) {
isoclns_print(ndo, p, length, caplen);
isoclns_print(ndo, p, length);
return (hdrlen);
}
-
+#endif
if (!ndo->ndo_eflag) {
if (ssap == dsap) {
@@ -480,6 +486,7 @@ snap_print(netdissect_options *ndo, cons
if (src == NULL || dst == NULL)
@@ -480,6 +485,7 @@ snap_print(netdissect_options *ndo, cons
case OUI_CISCO:
switch (et) {
@ -494,7 +498,7 @@
case PID_CISCO_CDP:
cdp_print(ndo, p, length, caplen);
return (1);
@@ -492,6 +499,7 @@ snap_print(netdissect_options *ndo, cons
@@ -492,6 +498,7 @@ snap_print(netdissect_options *ndo, cons
case PID_CISCO_VTP:
vtp_print(ndo, p, length);
return (1);
@ -502,7 +506,7 @@
case PID_CISCO_PVST:
case PID_CISCO_VLANBRIDGE:
stp_print(ndo, p, length);
@@ -504,6 +512,7 @@ snap_print(netdissect_options *ndo, cons
@@ -504,6 +511,7 @@ snap_print(netdissect_options *ndo, cons
case OUI_RFC2684:
switch (et) {
@ -510,7 +514,7 @@
case PID_RFC2684_ETH_FCS:
case PID_RFC2684_ETH_NOFCS:
/*
@@ -565,6 +574,7 @@ snap_print(netdissect_options *ndo, cons
@@ -565,6 +573,7 @@ snap_print(netdissect_options *ndo, cons
*/
fddi_print(ndo, p, length, caplen);
return (1);
@ -526,7 +530,7 @@
+#ifndef TCPDUMP_MINI
case BSD_AFNUM_ISO:
isoclns_print(ndo, p, length, caplen);
isoclns_print(ndo, p, length);
break;
@@ -127,6 +128,7 @@ null_if_print(netdissect_options *ndo, c
case BSD_AFNUM_IPX:
@ -538,7 +542,7 @@
/* unknown AF_ value */
--- a/print-ppp.c
+++ b/print-ppp.c
@@ -1358,6 +1358,7 @@ trunc:
@@ -1367,6 +1367,7 @@ trunc:
return 0;
}
@ -546,7 +550,7 @@
static void
ppp_hdlc(netdissect_options *ndo,
const u_char *p, int length)
@@ -1436,6 +1437,7 @@ trunc:
@@ -1445,6 +1446,7 @@ trunc:
free(b);
ND_PRINT((ndo, "[|ppp]"));
}
@ -554,7 +558,7 @@
/* PPP */
@@ -1443,10 +1445,12 @@ static void
@@ -1452,10 +1454,12 @@ static void
handle_ppp(netdissect_options *ndo,
u_int proto, const u_char *p, int length)
{
@ -567,7 +571,7 @@
switch (proto) {
case PPP_LCP: /* fall through */
@@ -1479,6 +1483,7 @@ handle_ppp(netdissect_options *ndo,
@@ -1488,6 +1492,7 @@ handle_ppp(netdissect_options *ndo,
case PPP_IPV6:
ip6_print(ndo, p, length);
break;
@ -575,7 +579,7 @@
case ETHERTYPE_IPX: /*XXX*/
case PPP_IPX:
ipx_print(ndo, p, length);
@@ -1490,6 +1495,7 @@ handle_ppp(netdissect_options *ndo,
@@ -1499,6 +1504,7 @@ handle_ppp(netdissect_options *ndo,
case PPP_MPLS_MCAST:
mpls_print(ndo, p, length);
break;
@ -583,7 +587,7 @@
case PPP_COMP:
ND_PRINT((ndo, "compressed PPP data"));
break;
@@ -1630,6 +1636,7 @@ ppp_if_print(netdissect_options *ndo,
@@ -1639,6 +1645,7 @@ ppp_if_print(netdissect_options *ndo,
return (0);
}
@ -591,7 +595,7 @@
/*
* PPP I/F printer to use if we know that RFC 1662-style PPP in HDLC-like
* framing, or Cisco PPP with HDLC framing as per section 4.3.1 of RFC 1547,
@@ -1857,6 +1864,7 @@ printx:
@@ -1866,6 +1873,7 @@ printx:
#endif /* __bsdi__ */
return (hdrlength);
}

View File

@ -207,7 +207,6 @@ foreach my $mirror (@ARGV) {
push @mirrors, "https://raw.githubusercontent.com/$1";
}
} elsif ($mirror =~ /^\@GNU\/(.+)$/) {
push @mirrors, "http://mirrors.ustc.edu.cn/gnu/$1";
push @mirrors, "https://mirror.csclub.uwaterloo.ca/gnu/$1";
push @mirrors, "https://mirror.netcologne.de/gnu/$1";
push @mirrors, "http://ftp.kddilabs.jp/GNU/gnu/$1";
@ -233,7 +232,6 @@ foreach my $mirror (@ARGV) {
push @extra, "$extra[0]/longterm/v$1";
}
foreach my $dir (@extra) {
push @mirrors, "http://mirrors.ustc.edu.cn/kernel.org/$dir";
push @mirrors, "https://cdn.kernel.org/pub/$dir";
push @mirrors, "https://mirror.rackspace.com/kernel.org/$dir";
push @mirrors, "http://download.xs4all.nl/ftp.kernel.org/pub/$dir";

View File

@ -53,6 +53,7 @@ ap121f)
ucidef_set_led_wlan "wlan" "WLAN" "$board:green:wlan" "phy0tpt"
;;
ap531b0|\
gl-usb150|\
sc1750|\
sc450)
ucidef_set_led_wlan "wlan" "WLAN" "$board:green:wlan" "phy0tpt"
@ -184,6 +185,7 @@ cf-e320n-v2)
ucidef_set_led_netdev "wan" "WAN" "$board:red:wan" "eth1"
ucidef_set_led_wlan "wlan" "WLAN" "$board:blue:wlan" "phy0tpt"
;;
cf-e355ac|\
cf-e380ac-v1|\
cf-e380ac-v2)
ucidef_set_led_netdev "lan" "LAN" "$board:green:lan" "eth0"
@ -823,7 +825,8 @@ r6100)
;;
wndr3700v4|\
wndr4300)
ucidef_set_led_netdev "wan" "WAN (green)" "netgear:green:wan" "eth0.2"
ucidef_set_led_switch "wan-green" "WAN (green)" "netgear:green:wan" "switch0" "0x20" "0x08"
ucidef_set_led_switch "wan-amber" "WAN (amber)" "netgear:amber:wan" "switch0" "0x20" "0x06"
ucidef_set_led_usbdev "usb" "USB" "netgear:green:usb" "1-1"
ucidef_set_led_wlan "wlan2g" "WLAN2G" "netgear:green:wlan2g" "phy0tpt"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "netgear:blue:wlan5g" "phy1tpt"

View File

@ -75,6 +75,7 @@ ar71xx_setup_interfaces()
eap7660d|\
el-mini|\
fritz300e|\
gl-usb150|\
hiveap-121|\
loco-m-xw|\
mr12|\
@ -539,7 +540,8 @@ ar71xx_setup_macs()
mynet-n750)
wan_mac=$(mtd_get_mac_ascii devdata "wanmac")
;;
wpj344)
wpj344|\
wpj558)
wan_mac=$(mtd_get_mac_binary u-boot 0x2e018)
;;
esac

View File

@ -59,6 +59,7 @@ get_status_led() {
archer-c59-v1|\
archer-c60-v1|\
fritz300e|\
gl-usb150|\
mr12|\
mr16|\
nbg6616|\

View File

@ -61,6 +61,7 @@ case "$FIRMWARE" in
ath10kcal_extract "art" 20480 2116
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) -2)
;;
cf-e355ac|\
cf-e380ac-v1|\
cf-e380ac-v2|\
dlan-pro-1200-ac|\

View File

@ -507,6 +507,9 @@ ar71xx_board_detect() {
*"CF-E320N v2")
name="cf-e320n-v2"
;;
*"CF-E355AC")
name="cf-e355ac"
;;
*"CF-E380AC v1")
name="cf-e380ac-v1"
;;
@ -672,6 +675,9 @@ ar71xx_board_detect() {
*"GL-MIFI")
name="gl-mifi"
;;
*"GL-USB150")
name="gl-usb150"
;;
*"HiveAP-121")
name="hiveap-121"
;;

View File

@ -216,6 +216,7 @@ platform_check_image() {
carambola2|\
cf-e316n-v2|\
cf-e320n-v2|\
cf-e355ac|\
cf-e380ac-v1|\
cf-e380ac-v2|\
cf-e520n|\
@ -250,6 +251,7 @@ platform_check_image() {
gl-ar300|\
gl-domino|\
gl-mifi|\
gl-usb150|\
hiwifi-hc6361|\
hornet-ub-x2|\
jwap230|\

View File

@ -69,6 +69,7 @@ CONFIG_ATH79_MACH_CAP4200AG=y
CONFIG_ATH79_MACH_CARAMBOLA2=y
CONFIG_ATH79_MACH_CF_E316N_V2=y
CONFIG_ATH79_MACH_CF_E320N_V2=y
CONFIG_ATH79_MACH_CF_E355AC=y
CONFIG_ATH79_MACH_CF_E380AC_V1=y
CONFIG_ATH79_MACH_CF_E380AC_V2=y
CONFIG_ATH79_MACH_CF_E520N=y
@ -116,6 +117,7 @@ CONFIG_ATH79_MACH_GL_AR300M=y
CONFIG_ATH79_MACH_GL_DOMINO=y
CONFIG_ATH79_MACH_GL_INET=y
CONFIG_ATH79_MACH_GL_MIFI=y
CONFIG_ATH79_MACH_GL_USB150=y
CONFIG_ATH79_MACH_GS_MINIBOX_V1=y
CONFIG_ATH79_MACH_GS_OOLITE=y
# CONFIG_ATH79_MACH_HIVEAP_121 is not set

View File

@ -768,6 +768,15 @@ config ATH79_MACH_GL_INET
select ATH79_DEV_USB
select ATH79_DEV_WMAC
config ATH79_MACH_GL_USB150
bool "GL.iNet GL-USB150 support"
select SOC_AR933X
select ATH79_DEV_ETH
select ATH79_DEV_GPIO_BUTTONS
select ATH79_DEV_LEDS_GPIO
select ATH79_DEV_M25P80
select ATH79_DEV_WMAC
config ATH79_MACH_EAP120
bool "TP-LINK EAP120 support"
select SOC_AR934X
@ -2019,6 +2028,14 @@ config ATH79_MACH_CF_E320N_V2
select ATH79_DEV_USB
select ATH79_DEV_WMAC
config ATH79_MACH_CF_E355AC
bool "COMFAST CF-E355AC support"
select SOC_QCA953X
select ATH79_DEV_ETH
select ATH79_DEV_GPIO_BUTTONS
select ATH79_DEV_AP9X_PCI if PCI
select ATH79_DEV_WMAC
config ATH79_MACH_CF_E380AC_V1
bool "COMFAST CF-E380AC v1 support"
select SOC_QCA955X

View File

@ -74,6 +74,7 @@ obj-$(CONFIG_ATH79_MACH_CAP4200AG) += mach-cap4200ag.o
obj-$(CONFIG_ATH79_MACH_CARAMBOLA2) += mach-carambola2.o
obj-$(CONFIG_ATH79_MACH_CF_E316N_V2) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CF_E320N_V2) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CF_E355AC) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CF_E380AC_V1) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CF_E380AC_V2) += mach-cf-e316n-v2.o
obj-$(CONFIG_ATH79_MACH_CF_E520N) += mach-cf-e316n-v2.o
@ -120,6 +121,7 @@ obj-$(CONFIG_ATH79_MACH_GL_AR300M) += mach-gl-ar300m.o
obj-$(CONFIG_ATH79_MACH_GL_DOMINO) += mach-gl-domino.o
obj-$(CONFIG_ATH79_MACH_GL_INET) += mach-gl-inet.o
obj-$(CONFIG_ATH79_MACH_GL_MIFI) += mach-gl-mifi.o
obj-$(CONFIG_ATH79_MACH_GL_USB150) += mach-gl-usb150.o
obj-$(CONFIG_ATH79_MACH_GS_MINIBOX_V1) += mach-gs-minibox-v1.o
obj-$(CONFIG_ATH79_MACH_GS_OOLITE) += mach-gs-oolite.o
obj-$(CONFIG_ATH79_MACH_HIVEAP_121) += mach-hiveap-121.o

View File

@ -2,6 +2,7 @@
* Support for COMFAST boards:
* - CF-E316N v2 (AR9341)
* - CF-E320N v2 (QCA9531)
* - CF-E355AC (QCA9531)
* - CF-E380AC v1/v2 (QCA9558)
* - CF-E520N/CF-E530N (QCA9531)
*
@ -130,6 +131,42 @@ static struct gpio_keys_button cf_e320n_v2_gpio_keys[] __initdata = {
},
};
/* CF-E355AC */
#define CF_E355AC_GPIO_LED_LAN 3
#define CF_E355AC_GPIO_LED_WLAN2G 0
#define CF_E355AC_GPIO_LED_WLAN5G 2
#define CF_E355AC_GPIO_EXT_WDT 13
#define CF_E355AC_GPIO_BTN_RESET 17
static struct gpio_led cf_e355ac_leds_gpio[] __initdata = {
{
.name = "cf-e355ac:green:lan",
.gpio = CF_E355AC_GPIO_LED_LAN,
.active_low = 0,
}, {
.name = "cf-e355ac:blue:wlan2g",
.gpio = CF_E355AC_GPIO_LED_WLAN2G,
.active_low = 0,
}, {
.name = "cf-e355ac:red:wlan5g",
.gpio = CF_E355AC_GPIO_LED_WLAN5G,
.active_low = 0,
},
};
static struct gpio_keys_button cf_e355ac_gpio_keys[] __initdata = {
{
.desc = "Reset button",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = CF_EXXXN_KEYS_DEBOUNCE_INTERVAL,
.gpio = CF_E355AC_GPIO_BTN_RESET,
.active_low = 1,
},
};
/* CF-E380AC v1/v2 */
#define CF_E380AC_V1V2_GPIO_LED_LAN 0
#define CF_E380AC_V1V2_GPIO_LED_WLAN2G 2
@ -355,6 +392,34 @@ static void __init cf_e320n_v2_setup(void)
MIPS_MACHINE(ATH79_MACH_CF_E320N_V2, "CF-E320N-V2", "COMFAST CF-E320N v2",
cf_e320n_v2_setup);
static void __init cf_e355ac_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1f010000);
/* Disable JTAG, enabling GPIOs 0-3 */
ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, 0);
cf_exxxn_common_setup(0x10000, CF_E355AC_GPIO_EXT_WDT);
cf_exxxn_qca953x_eth_setup();
ath79_gpio_output_select(CF_E355AC_GPIO_LED_LAN, 0);
ath79_gpio_output_select(CF_E355AC_GPIO_LED_WLAN2G, 0);
ath79_gpio_output_select(CF_E355AC_GPIO_LED_WLAN5G, 0);
ap91_pci_init(art + 0x5000, NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(cf_e355ac_leds_gpio),
cf_e355ac_leds_gpio);
ath79_register_gpio_keys_polled(1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e355ac_gpio_keys),
cf_e355ac_gpio_keys);
}
MIPS_MACHINE(ATH79_MACH_CF_E355AC, "CF-E355AC", "COMFAST CF-E355AC",
cf_e355ac_setup);
static void __init cf_e380ac_v1v2_common_setup(unsigned long art_ofs)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f000000 + art_ofs);

View File

@ -74,6 +74,22 @@ static struct gpio_keys_button tl_wr1041nv2_gpio_keys[] __initdata = {
}
};
static const struct ar8327_led_info tl_wr1041n_leds_ar8327[] = {
AR8327_LED_INFO(PHY0_0, HW, "tp-link:green:wan"),
AR8327_LED_INFO(PHY1_0, HW, "tp-link:green:lan1"),
AR8327_LED_INFO(PHY2_0, HW, "tp-link:green:lan2"),
AR8327_LED_INFO(PHY3_0, HW, "tp-link:green:lan3"),
AR8327_LED_INFO(PHY4_0, HW, "tp-link:green:lan4"),
};
static struct ar8327_led_cfg wr1041n_v2_ar8327_led_cfg = {
.led_ctrl0 = 0xcf35cf35, /* LED0: blink at 10/100/1000M */
.led_ctrl1 = 0xcf35cf35, /* LED1: blink at 10/100/1000M: anyway, no LED1 on tl-wr1041n */
.led_ctrl2 = 0xcf35cf35, /* LED2: blink at 10/100/1000M: anyway, no LED2 on tl-wr1041n */
.led_ctrl3 = 0x03ffff00, /* Pattern enabled for LED 0-2 of port 1-3 */
.open_drain = true,
};
static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
.mode = AR8327_PAD_MAC_RGMII,
.txclk_delay_en = true,
@ -90,7 +106,10 @@ static struct ar8327_platform_data db120_ar8327_data = {
.duplex = 1,
.txpause = 1,
.rxpause = 1,
}
},
.led_cfg = &wr1041n_v2_ar8327_led_cfg,
.num_leds = ARRAY_SIZE(tl_wr1041n_leds_ar8327),
.leds = tl_wr1041n_leds_ar8327
};
static struct mdio_board_info db120_mdio0_info[] = {

View File

@ -50,7 +50,7 @@
#define WPJ558_KEYS_POLL_INTERVAL 20 /* msecs */
#define WPJ558_KEYS_DEBOUNCE_INTERVAL (3 * WPJ558_KEYS_POLL_INTERVAL)
#define WPJ558_MAC_OFFSET 0x1002
#define WPJ558_MAC_OFFSET 0x10
#define WPJ558_WMAC_CALDATA_OFFSET 0x1000
static struct gpio_led wpj558_leds_gpio[] __initdata = {
@ -135,6 +135,7 @@ static struct mdio_board_info wpj558_mdio0_info[] = {
static void __init wpj558_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj558_leds_gpio),
@ -153,8 +154,7 @@ static void __init wpj558_setup(void)
ARRAY_SIZE(wpj558_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ558_MAC_OFFSET, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
@ -164,14 +164,7 @@ static void __init wpj558_setup(void)
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_register_eth(0);
ath79_register_eth(1);
}
MIPS_MACHINE(ATH79_MACH_WPJ558, "WPJ558", "Compex WPJ558", wpj558_setup);

View File

@ -60,6 +60,7 @@ enum ath79_mach_type {
ATH79_MACH_CARAMBOLA2, /* 8devices Carambola2 */
ATH79_MACH_CF_E316N_V2, /* COMFAST CF-E316N v2 */
ATH79_MACH_CF_E320N_V2, /* COMFAST CF-E320N v2 */
ATH79_MACH_CF_E355AC, /* COMFAST CF-E355AC */
ATH79_MACH_CF_E380AC_V1, /* COMFAST CF-E380AC v1 */
ATH79_MACH_CF_E380AC_V2, /* COMFAST CF-E380AC v2 */
ATH79_MACH_CF_E520N, /* COMFAST CF-E520N */
@ -112,6 +113,7 @@ enum ath79_mach_type {
ATH79_MACH_GL_DOMINO, /* Domino */
ATH79_MACH_GL_INET, /* GL-CONNECT GL-INET */
ATH79_MACH_GL_MIFI, /* GL-MIFI support */
ATH79_MACH_GL_USB150, /* GL.iNet GL-USB150 */
ATH79_MACH_GS_MINIBOX_V1, /* Gainstrong MiniBox V1.0 */
ATH79_MACH_GS_OOLITE, /* GS OOLITE V1.0 */
ATH79_MACH_HIVEAP_121, /* Aerohive HiveAP-121*/

View File

@ -151,6 +151,15 @@ define Device/cf-e320n-v2
endef
TARGET_DEVICES += cf-e320n-v2
define Device/cf-e355ac
DEVICE_TITLE := COMFAST CF-E355AC
DEVICE_PACKAGES := kmod-usb-core kmod-usb2 kmod-ath10k ath10k-firmware-qca988x
BOARDNAME := CF-E355AC
IMAGE_SIZE := 16192k
MTDPARTS := spi0.0:64k(u-boot)ro,64k(art)ro,16192k(firmware),64k(art-backup)ro
endef
TARGET_DEVICES += cf-e355ac
define Device/cf-e380ac-v1
DEVICE_TITLE := COMFAST CF-E380AC v1
DEVICE_PACKAGES := kmod-usb-core kmod-usb2 kmod-ath10k ath10k-firmware-qca988x
@ -278,6 +287,19 @@ define Device/gl-mifi
endef
TARGET_DEVICES += gl-mifi
define Device/gl-usb150
DEVICE_TITLE := GL.iNet GL-USB150
DEVICE_PACKAGES := -swconfig
BOARDNAME := GL-USB150
IMAGE_SIZE := 16000k
CONSOLE := ttyATH0,115200
MTDPARTS := spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,16000k(firmware),64k(art)ro
SUPPORTED_DEVICES := gl-usb150
IMAGE/sysupgrade.bin = append-kernel | pad-to $$$$(BLOCKSIZE) | \
append-rootfs | pad-rootfs | append-metadata | check-size $$$$(IMAGE_SIZE)
endef
TARGET_DEVICES += gl-usb150
define Device/lima
DEVICE_TITLE := 8devices Lima
DEVICE_PACKAGES := kmod-usb-core kmod-usb2
@ -852,6 +874,9 @@ define Device/wpj344
$(Device/wpj-16m)
DEVICE_TITLE := Compex WPJ344 (16MB flash)
BOARDNAME := WPJ344
SUPPORTED_DEVICES := wpj344
IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \
append-rootfs | pad-rootfs | append-metadata | check-size $$$$(IMAGE_SIZE)
endef
define Device/wpj531
@ -864,6 +889,9 @@ define Device/wpj558
$(Device/wpj-16m)
DEVICE_TITLE := Compex WPJ558 (16MB flash)
BOARDNAME := WPJ558
SUPPORTED_DEVICES := wpj558
IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \
append-rootfs | pad-rootfs | append-metadata | check-size $$$$(IMAGE_SIZE)
endef
define Device/wpj563

View File

@ -34,6 +34,7 @@
# CONFIG_ATH79_MACH_CARAMBOLA2 is not set
# CONFIG_ATH79_MACH_CF_E316N_V2 is not set
# CONFIG_ATH79_MACH_CF_E320N_V2 is not set
# CONFIG_ATH79_MACH_CF_E355AC is not set
# CONFIG_ATH79_MACH_CF_E380AC_V1 is not set
# CONFIG_ATH79_MACH_CF_E380AC_V2 is not set
# CONFIG_ATH79_MACH_CF_E520N is not set
@ -80,6 +81,7 @@
# CONFIG_ATH79_MACH_GL_DOMINO is not set
# CONFIG_ATH79_MACH_GL_INET is not set
# CONFIG_ATH79_MACH_GL_MIFI is not set
# CONFIG_ATH79_MACH_GL_USB150 is not set
# CONFIG_ATH79_MACH_GS_MINIBOX_V1 is not set
# CONFIG_ATH79_MACH_GS_OOLITE is not set
# CONFIG_ATH79_MACH_HIWIFI_HC6361 is not set

View File

@ -34,6 +34,7 @@ CONFIG_ATH79_MACH_C60=y
# CONFIG_ATH79_MACH_CARAMBOLA2 is not set
# CONFIG_ATH79_MACH_CF_E316N_V2 is not set
# CONFIG_ATH79_MACH_CF_E320N_V2 is not set
# CONFIG_ATH79_MACH_CF_E355AC is not set
# CONFIG_ATH79_MACH_CF_E380AC_V1 is not set
# CONFIG_ATH79_MACH_CF_E380AC_V2 is not set
# CONFIG_ATH79_MACH_CF_E520N is not set
@ -81,6 +82,7 @@ CONFIG_ATH79_MACH_DOMYWIFI_DW33D=y
# CONFIG_ATH79_MACH_GL_DOMINO is not set
# CONFIG_ATH79_MACH_GL_INET is not set
# CONFIG_ATH79_MACH_GL_MIFI is not set
# CONFIG_ATH79_MACH_GL_USB150 is not set
# CONFIG_ATH79_MACH_GS_MINIBOX_V1 is not set
# CONFIG_ATH79_MACH_GS_OOLITE is not set
CONFIG_ATH79_MACH_HIVEAP_121=y

View File

@ -21,7 +21,7 @@ Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
#include "b53_regs.h"
#include "b53_priv.h"
@@ -1522,6 +1523,28 @@ static int b53_switch_init(struct b53_de
@@ -1578,6 +1579,28 @@ static int b53_switch_init(struct b53_de
return ret;
}

View File

@ -20,7 +20,7 @@ Subject: [PATCH 6/8] * [rtl8367r] Fix RGMII support
#define RTL8367_DI_FORCE_REG(_x) (0x1310 + (_x))
#define RTL8367_DI_FORCE_MODE BIT(12)
#define RTL8367_DI_FORCE_NWAY BIT(7)
@@ -894,6 +898,7 @@ static int rtl8367_extif_set_mode(struct
@@ -897,6 +901,7 @@ static int rtl8367_extif_set_mode(struct
case RTL8367_EXTIF_MODE_RGMII_33V:
REG_WR(smi, RTL8367_CHIP_DEBUG0_REG, 0x0367);
REG_WR(smi, RTL8367_CHIP_DEBUG1_REG, 0x7777);

View File

@ -592,7 +592,11 @@ rtl_get_port_link(struct switch_dev *dev, int port, struct switch_port_link *lin
if (port >= RTL8306_NUM_PORTS)
return -EINVAL;
/* in case the link changes from down to up, the register is only updated on read */
link->link = rtl_get(dev, RTL_PORT_REG(port, LINK));
if (!link->link)
link->link = rtl_get(dev, RTL_PORT_REG(port, LINK));
if (!link->link)
return 0;

View File

@ -1,6 +1,6 @@
--- a/drivers/net/phy/adm6996.c
+++ b/drivers/net/phy/adm6996.c
@@ -286,7 +286,7 @@ static u16
@@ -289,7 +289,7 @@ static u16
adm6996_read_mii_reg(struct adm6996_priv *priv, enum admreg reg)
{
struct phy_device *phydev = priv->priv;
@ -9,7 +9,7 @@
return bus->read(bus, PHYADDR(reg));
}
@@ -295,7 +295,7 @@ static void
@@ -298,7 +298,7 @@ static void
adm6996_write_mii_reg(struct adm6996_priv *priv, enum admreg reg, u16 val)
{
struct phy_device *phydev = priv->priv;
@ -18,7 +18,7 @@
bus->write(bus, PHYADDR(reg), val);
}
@@ -1018,13 +1018,13 @@ static int adm6996_config_init(struct ph
@@ -1050,13 +1050,13 @@ static int adm6996_config_init(struct ph
pdev->supported = ADVERTISED_100baseT_Full;
pdev->advertising = ADVERTISED_100baseT_Full;
@ -35,7 +35,7 @@
if (!priv)
return -ENOMEM;
@@ -1044,7 +1044,7 @@ static int adm6996_config_init(struct ph
@@ -1076,7 +1076,7 @@ static int adm6996_config_init(struct ph
}
/*
@ -44,7 +44,7 @@
*/
static int adm6996_read_status(struct phy_device *phydev)
{
@@ -1060,7 +1060,7 @@ static int adm6996_read_status(struct ph
@@ -1092,7 +1092,7 @@ static int adm6996_read_status(struct ph
}
/*
@ -53,7 +53,7 @@
*/
static int adm6996_config_aneg(struct phy_device *phydev)
{
@@ -1069,11 +1069,11 @@ static int adm6996_config_aneg(struct ph
@@ -1101,11 +1101,11 @@ static int adm6996_config_aneg(struct ph
static int adm6996_fixup(struct phy_device *dev)
{
@ -67,7 +67,7 @@
return 0;
/* look for the switch on the bus */
@@ -1120,6 +1120,7 @@ static struct phy_driver adm6996_phy_dri
@@ -1152,6 +1152,7 @@ static struct phy_driver adm6996_phy_dri
.config_aneg = &adm6996_config_aneg,
.read_status = &adm6996_read_status,
.soft_reset = adm6996_soft_reset,
@ -75,7 +75,7 @@
};
static int adm6996_gpio_probe(struct platform_device *pdev)
@@ -1188,7 +1189,7 @@ static int __init adm6996_init(void)
@@ -1220,7 +1221,7 @@ static int __init adm6996_init(void)
int err;
phy_register_fixup_for_id(PHY_ANY_ID, adm6996_fixup);
@ -86,7 +86,7 @@
--- a/drivers/net/phy/ar8216.c
+++ b/drivers/net/phy/ar8216.c
@@ -177,7 +177,7 @@ ar8xxx_phy_check_aneg(struct phy_device
@@ -183,7 +183,7 @@ ar8xxx_phy_check_aneg(struct phy_device
if (ret & BMCR_ANENABLE)
return 0;
@ -95,7 +95,7 @@
ret |= BMCR_ANENABLE | BMCR_ANRESTART;
return phy_write(phydev, MII_BMCR, ret);
}
@@ -1997,7 +1997,7 @@ ar8xxx_phy_config_init(struct phy_device
@@ -2054,7 +2054,7 @@ ar8xxx_phy_config_init(struct phy_device
priv->phy = phydev;
@ -104,7 +104,7 @@
if (chip_is_ar8316(priv)) {
/* switch device has been initialized, reinit */
priv->dev.ports = (AR8216_NUM_PORTS - 1);
@@ -2045,7 +2045,7 @@ ar8xxx_check_link_states(struct ar8xxx_p
@@ -2102,7 +2102,7 @@ ar8xxx_check_link_states(struct ar8xxx_p
/* flush ARL entries for this port if it went down*/
if (!link_new)
priv->chip->atu_flush_port(priv, i);
@ -113,7 +113,7 @@
i, link_new ? "up" : "down");
}
@@ -2064,10 +2064,10 @@ ar8xxx_phy_read_status(struct phy_device
@@ -2121,10 +2121,10 @@ ar8xxx_phy_read_status(struct phy_device
if (phydev->state == PHY_CHANGELINK)
ar8xxx_check_link_states(priv);
@ -126,7 +126,7 @@
phydev->link = !!link.link;
if (!phydev->link)
return 0;
@@ -2097,7 +2097,7 @@ ar8xxx_phy_read_status(struct phy_device
@@ -2154,7 +2154,7 @@ ar8xxx_phy_read_status(struct phy_device
static int
ar8xxx_phy_config_aneg(struct phy_device *phydev)
{
@ -135,7 +135,7 @@
return 0;
return genphy_config_aneg(phydev);
@@ -2152,15 +2152,15 @@ ar8xxx_phy_probe(struct phy_device *phyd
@@ -2209,15 +2209,15 @@ ar8xxx_phy_probe(struct phy_device *phyd
int ret;
/* skip PHYs at unused adresses */
@ -154,7 +154,7 @@
goto found;
priv = ar8xxx_create();
@@ -2169,7 +2169,7 @@ ar8xxx_phy_probe(struct phy_device *phyd
@@ -2226,7 +2226,7 @@ ar8xxx_phy_probe(struct phy_device *phyd
goto unlock;
}
@ -163,7 +163,7 @@
ret = ar8xxx_probe_switch(priv);
if (ret)
@@ -2190,7 +2190,7 @@ ar8xxx_phy_probe(struct phy_device *phyd
@@ -2247,7 +2247,7 @@ ar8xxx_phy_probe(struct phy_device *phyd
found:
priv->use_count++;
@ -172,7 +172,7 @@
if (ar8xxx_has_gige(priv)) {
phydev->supported = SUPPORTED_1000baseT_Full;
phydev->advertising = ADVERTISED_1000baseT_Full;
@@ -2278,21 +2278,33 @@ ar8xxx_phy_soft_reset(struct phy_device
@@ -2335,21 +2335,33 @@ ar8xxx_phy_soft_reset(struct phy_device
return 0;
}

View File

@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
static struct amd_chipset_info {
struct pci_dev *nb_dev;
struct pci_dev *smbus_dev;
@@ -510,6 +512,10 @@ void usb_amd_dev_put(void)
@@ -511,6 +513,10 @@ void usb_amd_dev_put(void)
}
EXPORT_SYMBOL_GPL(usb_amd_dev_put);
@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
/*
* Make sure the controller is completely inactive, unable to
* generate interrupts or do DMA.
@@ -589,8 +595,17 @@ reset_needed:
@@ -590,8 +596,17 @@ reset_needed:
uhci_reset_hc(pdev, base);
return 1;
}
@ -48,7 +48,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
{
u16 cmd;
@@ -1157,3 +1172,4 @@ static void quirk_usb_early_handoff(stru
@@ -1158,3 +1173,4 @@ static void quirk_usb_early_handoff(stru
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);

View File

@ -1,448 +0,0 @@
#include "qcom-ipq8064-v1.0.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Buffalo WXR-2533DHP";
compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
aliases {
serial0 = &uart4;
mdio-gpio0 = &mdio0;
led-boot = &power_white;
led-failsafe = &power_orange;
led-running = &power_white;
led-upgrade = &power_orange;
};
chosen {
bootargs = "console=ttyMSM0,115200n8 ubi.mtd=0 ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs";
linux,stdout-path = "serial0:115200n8";
};
soc {
pinmux@800000 {
i2c4_pins: i2c4_pinmux {
mux {
pins = "gpio12", "gpio13";
function = "gsbi4";
drive-strength = <12>;
bias-disable;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
drive-strength = <10>;
bias-none;
};
};
nand_pins: nand_pins {
mux {
pins = "gpio34", "gpio35", "gpio36",
"gpio37", "gpio38", "gpio39",
"gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45",
"gpio46", "gpio47";
function = "nand";
drive-strength = <10>;
bias-disable;
};
pullups {
pins = "gpio39";
bias-pull-up;
};
hold {
pins = "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45",
"gpio46", "gpio47";
bias-bus-hold;
};
};
mdio0_pins: mdio0_pins {
mux {
pins = "gpio0", "gpio1";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
};
rgmii2_pins: rgmii2_pins {
mux {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
function = "rgmii2";
drive-strength = <8>;
bias-disable;
};
};
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22", "gpio23",
"gpio24", "gpio25", "gpio26", "gpio53";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
button_pins: button_pins {
mux {
pins = "gpio54", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
nand@1ac00000 {
status = "ok";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
cs0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
rootfs@0000000 {
label = "rootfs";
reg = <0x0000000 0x4000000>;
};
rootfs_1@4000000 {
label = "rootfs_1";
reg = <0x4000000 0x4000000>;
};
};
};
};
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "ok";
uart4: serial@16340000 {
status = "ok";
};
/*
* The i2c device on gsbi4 should not be enabled.
* On ipq806x designs gsbi4 i2c is meant for exclusive
* RPM usage. Turning this on in kernel manifests as
* i2c failure for the RPM.
*/
};
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
status = "ok";
spi5: spi@1a280000 {
status = "ok";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
flash: m25p80@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
SBL1@0 {
label = "SBL1";
reg = <0x0 0x10000>;
read-only;
};
MIBIB@10000 {
label = "MIBIB";
reg = <0x10000 0x20000>;
read-only;
};
SBL2@30000 {
label = "SBL2";
reg = <0x30000 0x30000>;
read-only;
};
SBL3@60000 {
label = "SBL3";
reg = <0x60000 0x30000>;
read-only;
};
DDRCONFIG@90000 {
label = "DDRCONFIG";
reg = <0x90000 0x10000>;
read-only;
};
SSD@a0000 {
label = "SSD";
reg = <0xa0000 0x10000>;
read-only;
};
TZ@b0000 {
label = "TZ";
reg = <0xb0000 0x30000>;
read-only;
};
RPM@e0000 {
label = "RPM";
reg = <0xe0000 0x20000>;
read-only;
};
APPSBL@100000 {
label = "APPSBL";
reg = <0x100000 0x70000>;
read-only;
};
APPSBLENV@170000 {
label = "APPSBLENV";
reg = <0x170000 0x10000>;
read-only;
};
ART: ART@180000 {
label = "ART";
reg = <0x180000 0x40000>;
read-only;
};
BOOTCONFIG@1c0000 {
label = "OLDART";
reg = <0x1c0000 0x10000>;
read-only;
};
APPSBL_1@1d0000 {
label = "APPSBL_1";
reg = <0x1d0000 0x70000>;
};
};
};
};
phy@100f8800 { /* USB3 port 1 HS phy */
status = "ok";
};
phy@100f8830 { /* USB3 port 1 SS phy */
status = "ok";
};
phy@110f8800 { /* USB3 port 0 HS phy */
status = "ok";
};
phy@110f8830 { /* USB3 port 0 SS phy */
status = "ok";
};
usb30@0 {
status = "ok";
};
usb30@1 {
status = "ok";
};
pcie0: pci@1b500000 {
status = "ok";
phy-tx0-term-offset = <7>;
};
pcie1: pci@1b700000 {
status = "ok";
phy-tx0-term-offset = <7>;
};
mdio0: mdio {
compatible = "virtual,mdio-gpio";
#address-cells = <1>;
#size-cells = <0>;
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
device_type = "ethernet-phy";
reg = <0>;
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x000e4 0x6a545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
>;
};
phy4: ethernet-phy@4 {
device_type = "ethernet-phy";
reg = <4>;
};
};
gmac1: ethernet@37200000 {
status = "ok";
phy-mode = "rgmii";
qcom,id = <1>;
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,rgmii_delay = <0>;
qcom,emulation = <0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mtd-mac-address = <&ART 6>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
//lan
gmac2: ethernet@37400000 {
status = "ok";
phy-mode = "sgmii";
qcom,id = <2>;
qcom,phy_mdio_addr = <0>; /* none */
qcom,poll_required = <0>; /* no polling */
qcom,rgmii_delay = <0>;
qcom,emulation = <0>;
mtd-mac-address = <&ART 0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
rpm@108000 {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
aoss {
label = "aoss";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
power_white: power_white {
label = "wxr-2533dhp:white:power";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
power_orange: power_orange {
label = "wxr-2533dhp:orange:power";
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
wireless_white: wireless_white {
label = "wxr-2533dhp:white:wireless";
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
};
wireless_orange: wireless_orange {
label = "wxr-2533dhp:orange:wireless";
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
internet_white: internet_white {
label = "wxr-2533dhp:white:internet";
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
};
internet_orange: internet_orange {
label = "wxr-2533dhp:orange:internet";
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
};
router_white: router_white {
label = "wxr-2533dhp:white:router";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
};
router_orange: router_orange {
label = "wxr-2533dhp:orange:router";
gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
};
usb_green: usb_green {
label = "wxr-2533dhp:green:usb";
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
guest_green: guest_green {
label = "wxr-2533dhp:green:guest";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
};
};
&adm_dma {
status = "ok";
};

View File

@ -295,4 +295,6 @@ endef
TARGET_DEVICES += AP148 AP148-legacy C2600 D7800 DB149 EA8500 FRITZ4040 R7500 \
R7500v2 R7800 RT-AC58U NBG6817 VR2600v AP-DK04.1-C1
.NOTPARALLEL:
$(eval $(call BuildImage))

View File

@ -12,7 +12,7 @@ FEATURES:=squashfs
SUBTARGETS:=xrx200 xway xway_legacy falcon ase
MAINTAINER:=John Crispin <john@phrozen.org>
KERNEL_PATCHVER:=4.4
KERNEL_PATCHVER:=4.9
define Target/Description
Build firmware images for Lantiq SoC

View File

@ -1,204 +0,0 @@
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
# CONFIG_ARCH_HAS_SG_CHAIN is not set
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_CEVT_R4K=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_MIPS32=y
# CONFIG_CPU_MIPS32_R1 is not set
CONFIG_CPU_MIPS32_R2=y
CONFIG_CPU_MIPSR2=y
CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
CONFIG_CPU_R4K_CACHE_TLB=y
CONFIG_CPU_R4K_FPU=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_CPU_SUPPORTS_MSA=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CSRC_R4K=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_DTC=y
# CONFIG_DT_EASY50712 is not set
CONFIG_EARLY_PRINTK=y
CONFIG_ETHERNET_PACKET_MANGLE=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_DEVRES=y
CONFIG_GPIO_MM_LANTIQ=y
CONFIG_GPIO_STP_XWAY=y
CONFIG_GPIO_SYSFS=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
# CONFIG_HAVE_ARCH_BITREVERSE is not set
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_HAVE_BPF_JIT=y
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_HAVE_MACH_CLKDEV=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
CONFIG_HZ=250
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
CONFIG_HZ_PERIODIC=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MIPS_CPU=y
CONFIG_IRQ_WORK=y
CONFIG_LANTIQ=y
CONFIG_LANTIQ_DT_NONE=y
CONFIG_LANTIQ_ETOP=y
CONFIG_LANTIQ_WDT=y
# CONFIG_LANTIQ_XRX200 is not set
CONFIG_LEDS_GPIO=y
CONFIG_LIBFDT=y
CONFIG_MDIO_BOARDINFO=y
CONFIG_MIPS=y
CONFIG_MIPS_CLOCK_VSYSCALL=y
# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_MIPS_CMDLINE_FROM_DTB=y
# CONFIG_MIPS_ELF_APPENDED_DTB is not set
# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_MACHINE is not set
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_NO_APPENDED_DTB is not set
CONFIG_MIPS_RAW_APPENDED_DTB=y
CONFIG_MIPS_SPRAM=y
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_LANTIQ=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
CONFIG_MTD_SPLIT_EVA_FW=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_TPLINK_FW=y
CONFIG_MTD_SPLIT_UIMAGE_FW=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
# CONFIG_NO_IOPORT_MAP is not set
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_ADDRESS_PCI=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_MDIO=y
CONFIG_OF_MTD=y
CONFIG_OF_NET=y
CONFIG_OF_PCI=y
CONFIG_OF_PCI_IRQ=y
CONFIG_PCI=y
# CONFIG_PCIE_LANTIQ is not set
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_LANTIQ=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_LANTIQ=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PINCTRL_XWAY=y
CONFIG_PSB6970_PHY=y
# CONFIG_RCU_STALL_COMMON is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RTL8366RB_PHY=y
CONFIG_RTL8366_SMI=y
# CONFIG_SCHED_INFO is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SENSORS_LTQ_CPUTEMP is not set
# CONFIG_SERIAL_8250 is not set
CONFIG_SERIAL_LANTIQ=y
# CONFIG_SOC_AMAZON_SE is not set
# CONFIG_SOC_FALCON is not set
CONFIG_SOC_TYPE_XWAY=y
CONFIG_SOC_XWAY=y
CONFIG_SPI=y
CONFIG_SPI_LANTIQ=y
CONFIG_SPI_MASTER=y
CONFIG_SRCU=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_SWCONFIG=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_SYS_SUPPORTS_MULTITHREADING=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_USE_OF=y
# CONFIG_XRX200_PHY_FW is not set
CONFIG_ZONE_DMA_FLAG=0

View File

@ -91,7 +91,8 @@
};
pcie@d900000 {
status = "disabled";
status = "okay";
gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
};
};

View File

@ -78,6 +78,11 @@
status = "okay";
gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;
};
pci0: pci@E105400 {
status = "okay";
gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
};
};
gphy-xrx200 {

View File

@ -1,500 +0,0 @@
From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 3 Aug 2012 10:27:25 +0200
Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++
arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++
arch/mips/lantiq/irq.c | 2 +
arch/mips/mm/cache.c | 2 +
include/uapi/linux/atm.h | 6 +
net/atm/common.c | 6 +
net/atm/proc.c | 2 +-
7 files changed, 416 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
@@ -0,0 +1,196 @@
+/******************************************************************************
+**
+** FILE NAME : ifx_atm.h
+** PROJECT : UEIP
+** MODULES : ATM
+**
+** DATE : 17 Jun 2009
+** AUTHOR : Xu Liang
+** DESCRIPTION : Global ATM driver header file
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Date $Author $Comment
+** 07 JUL 2009 Xu Liang Init Version
+*******************************************************************************/
+
+#ifndef IFX_ATM_H
+#define IFX_ATM_H
+
+
+
+/*!
+ \defgroup IFX_ATM UEIP Project - ATM driver module
+ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
+ */
+
+/*!
+ \defgroup IFX_ATM_IOCTL IOCTL Commands
+ \ingroup IFX_ATM
+ \brief IOCTL Commands used by user application.
+ */
+
+/*!
+ \defgroup IFX_ATM_STRUCT Structures
+ \ingroup IFX_ATM
+ \brief Structures used by user application.
+ */
+
+/*!
+ \file ifx_atm.h
+ \ingroup IFX_ATM
+ \brief ATM driver header file
+ */
+
+
+
+/*
+ * ####################################
+ * Definition
+ * ####################################
+ */
+
+/*!
+ \addtogroup IFX_ATM_STRUCT
+ */
+/*@{*/
+
+/*
+ * ATM MIB
+ */
+
+/*!
+ \struct atm_cell_ifEntry_t
+ \brief Structure used for Cell Level MIB Counters.
+
+ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
+ */
+typedef struct {
+ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
+ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
+ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
+ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
+ __u32 ifInErrors; /*!< counter of error ingress cells */
+ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
+ __u32 ifOutErrors; /*!< counter of error egress cells */
+} atm_cell_ifEntry_t;
+
+/*!
+ \struct atm_aal5_ifEntry_t
+ \brief Structure used for AAL5 Frame Level MIB Counters.
+
+ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
+ */
+typedef struct {
+ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
+ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
+ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
+ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
+ __u32 ifInUcastPkts; /*!< counter of ingress packets */
+ __u32 ifOutUcastPkts; /*!< counter of egress packets */
+ __u32 ifInErrors; /*!< counter of error ingress packets */
+ __u32 ifInDiscards; /*!< counter of dropped ingress packets */
+ __u32 ifOutErros; /*!< counter of error egress packets */
+ __u32 ifOutDiscards; /*!< counter of dropped egress packets */
+} atm_aal5_ifEntry_t;
+
+/*!
+ \struct atm_aal5_vcc_t
+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
+
+ This structure is a part of structure "atm_aal5_vcc_x_t".
+ */
+typedef struct {
+ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
+ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
+ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
+} atm_aal5_vcc_t;
+
+/*!
+ \struct atm_aal5_vcc_x_t
+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
+
+ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
+ */
+typedef struct {
+ int vpi; /*!< VPI of the VCC to get MIB counters */
+ int vci; /*!< VCI of the VCC to get MIB counters */
+ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
+} atm_aal5_vcc_x_t;
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ * IOCTL
+ * ####################################
+ */
+
+/*!
+ \addtogroup IFX_ATM_IOCTL
+ */
+/*@{*/
+
+/*
+ * ioctl Command
+ */
+/*!
+ \brief ATM IOCTL Magic Number
+ */
+#define PPE_ATM_IOC_MAGIC 'o'
+/*!
+ \brief ATM IOCTL Command - Get Cell Level MIB Counters
+
+ This command is obsolete. User can get cell level MIB from DSL API.
+ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
+ */
+#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
+/*!
+ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
+
+ Get AAL5 packet counters.
+ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
+ */
+#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
+/*!
+ \brief ATM IOCTL Command - Get Per PVC MIB Counters
+
+ Get AAL5 packet counters for each PVC.
+ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
+ */
+#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
+/*!
+ \brief Total Number of ATM IOCTL Commands
+ */
+#define PPE_ATM_IOC_MAXNR 3
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ * API
+ * ####################################
+ */
+
+#ifdef __KERNEL__
+struct port_cell_info {
+ unsigned int port_num;
+ unsigned int tx_link_rate[2];
+};
+#endif
+
+
+
+#endif // IFX_ATM_H
+
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
@@ -0,0 +1,203 @@
+/******************************************************************************
+**
+** FILE NAME : ifx_ptm.h
+** PROJECT : UEIP
+** MODULES : PTM
+**
+** DATE : 17 Jun 2009
+** AUTHOR : Xu Liang
+** DESCRIPTION : Global PTM driver header file
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Date $Author $Comment
+** 07 JUL 2009 Xu Liang Init Version
+*******************************************************************************/
+
+#ifndef IFX_PTM_H
+#define IFX_PTM_H
+
+
+
+/*!
+ \defgroup IFX_PTM UEIP Project - PTM driver module
+ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
+ */
+
+/*!
+ \defgroup IFX_PTM_IOCTL IOCTL Commands
+ \ingroup IFX_PTM
+ \brief IOCTL Commands used by user application.
+ */
+
+/*!
+ \defgroup IFX_PTM_STRUCT Structures
+ \ingroup IFX_PTM
+ \brief Structures used by user application.
+ */
+
+/*!
+ \file ifx_ptm.h
+ \ingroup IFX_PTM
+ \brief PTM driver header file
+ */
+
+
+
+/*
+ * ####################################
+ * Definition
+ * ####################################
+ */
+
+
+
+/*
+ * ####################################
+ * IOCTL
+ * ####################################
+ */
+
+/*!
+ \addtogroup IFX_PTM_IOCTL
+ */
+/*@{*/
+
+/*
+ * ioctl Command
+ */
+/*!
+ \brief PTM IOCTL Command - Get codeword MIB counters.
+
+ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
+ */
+#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1
+/*!
+ \brief PTM IOCTL Command - Get packet MIB counters.
+
+ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
+ */
+#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2
+/*!
+ \brief PTM IOCTL Command - Get firmware configuration (CRC).
+
+ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
+ */
+#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3
+/*!
+ \brief PTM IOCTL Command - Set firmware configuration (CRC).
+
+ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
+ */
+#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4
+/*!
+ \brief PTM IOCTL Command - Program priority value to TX queue mapping.
+
+ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
+ */
+#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14
+
+/*@}*/
+
+
+/*!
+ \addtogroup IFX_PTM_STRUCT
+ */
+/*@{*/
+
+/*
+ * ioctl Data Type
+ */
+
+/*!
+ \typedef PTM_CW_IF_ENTRY_T
+ \brief Wrapping of structure "ptm_cw_ifEntry_t".
+ */
+/*!
+ \struct ptm_cw_ifEntry_t
+ \brief Structure used for CodeWord level MIB counters.
+ */
+typedef struct ptm_cw_ifEntry_t {
+ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */
+ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */
+ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */
+ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */
+ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */
+} PTM_CW_IF_ENTRY_T;
+
+/*!
+ \typedef PTM_FRAME_MIB_T
+ \brief Wrapping of structure "ptm_frame_mib_t".
+ */
+/*!
+ \struct ptm_frame_mib_t
+ \brief Structure used for packet level MIB counters.
+ */
+typedef struct ptm_frame_mib_t {
+ uint32_t RxCorrect; /*!< output, number of ingress packet */
+ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */
+ uint32_t RxDropped; /*!< output, number of dropped ingress packet */
+ uint32_t TxSend; /*!< output, number of egress packet */
+} PTM_FRAME_MIB_T;
+
+/*!
+ \typedef IFX_PTM_CFG_T
+ \brief Wrapping of structure "ptm_cfg_t".
+ */
+/*!
+ \struct ptm_cfg_t
+ \brief Structure used for ETH/TC CRC configuration.
+ */
+typedef struct ptm_cfg_t {
+ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */
+ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */
+ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */
+ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */
+ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */
+ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */
+ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */
+} IFX_PTM_CFG_T;
+
+/*!
+ \typedef IFX_PTM_PRIO_Q_MAP_T
+ \brief Wrapping of structure "ppe_prio_q_map".
+ */
+/*!
+ \struct ppe_prio_q_map
+ \brief Structure used for Priority Value to TX Queue mapping.
+ */
+typedef struct ppe_prio_q_map {
+ int pkt_prio;
+ int qid;
+ int vpi; // ignored in eth interface
+ int vci; // ignored in eth interface
+} IFX_PTM_PRIO_Q_MAP_T;
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ * API
+ * ####################################
+ */
+
+#ifdef __KERNEL__
+struct port_cell_info {
+ unsigned int port_num;
+ unsigned int tx_link_rate[2];
+};
+#endif
+
+
+
+#endif // IFX_PTM_H
+
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -14,6 +14,7 @@
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/module.h>
#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>
@@ -100,6 +101,7 @@ void ltq_mask_and_ack_irq(struct irq_dat
ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
ltq_icu_w32(im, BIT(offset), isr);
}
+EXPORT_SYMBOL(ltq_mask_and_ack_irq);
static void ltq_ack_irq(struct irq_data *d)
{
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -59,6 +59,8 @@ void (*_dma_cache_wback)(unsigned long s
void (*_dma_cache_inv)(unsigned long start, unsigned long size);
EXPORT_SYMBOL(_dma_cache_wback_inv);
+EXPORT_SYMBOL(_dma_cache_wback);
+EXPORT_SYMBOL(_dma_cache_inv);
#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
--- a/include/uapi/linux/atm.h
+++ b/include/uapi/linux/atm.h
@@ -130,8 +130,14 @@
#define ATM_ABR 4
#define ATM_ANYCLASS 5 /* compatible with everything */
+#define ATM_VBR_NRT ATM_VBR
+#define ATM_VBR_RT 6
+#define ATM_UBR_PLUS 7
+#define ATM_GFR 8
+
#define ATM_MAX_PCR -1 /* maximum available PCR */
+
struct atm_trafprm {
unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
int max_pcr; /* maximum PCR in cells per second */
--- a/net/atm/common.c
+++ b/net/atm/common.c
@@ -62,11 +62,17 @@ static void vcc_remove_socket(struct soc
write_unlock_irq(&vcc_sklist_lock);
}
+struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
+EXPORT_SYMBOL(ifx_atm_alloc_tx);
+
static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
{
struct sk_buff *skb;
struct sock *sk = sk_atm(vcc);
+ if (ifx_atm_alloc_tx != NULL)
+ return ifx_atm_alloc_tx(vcc, size);
+
if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
--- a/net/atm/proc.c
+++ b/net/atm/proc.c
@@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_fil
static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
{
static const char *const class_name[] = {
- "off", "UBR", "CBR", "VBR", "ABR"};
+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
static const char *const aal_name[] = {
"---", "1", "2", "3/4", /* 0- 3 */
"???", "5", "???", "???", /* 4- 7 */

View File

@ -1,68 +0,0 @@
From 25494c55a4007a1409f53ddbafd661636e47ea34 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 9 Aug 2013 20:38:15 +0200
Subject: [PATCH 12/36] pinctrl/lantiq: fix up pinmux
We found out how to set the gphy led pinmuxing.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/pinctrl/pinctrl-xway.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -609,10 +609,9 @@ static struct pinctrl_desc xway_pctrl_de
.confops = &xway_pinconf_ops,
};
-static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
+static int mux_apply(struct ltq_pinmux_info *info,
int pin, int mux)
{
- struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
int port = PORT(pin);
u32 alt1_reg = GPIO_ALT1(pin);
@@ -632,6 +631,14 @@ static inline int xway_mux_apply(struct
return 0;
}
+static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
+ int pin, int mux)
+{
+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
+
+ return mux_apply(info, pin, mux);
+}
+
static const struct ltq_cfg_param xway_cfg_params[] = {
{"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
{"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
@@ -682,6 +689,18 @@ static int xway_gpio_dir_out(struct gpio
return 0;
}
+static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
+ int i;
+
+ for (i = 0; i < info->num_exin; i++)
+ if (info->exin[i] == offset)
+ return ltq_eiu_get_irq(i);
+
+ return -1;
+}
+
static struct gpio_chip xway_chip = {
.label = "gpio-xway",
.direction_input = xway_gpio_dir_in,
@@ -690,6 +709,7 @@ static struct gpio_chip xway_chip = {
.set = xway_gpio_set,
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
+ .to_irq = xway_gpio_to_irq,
.base = -1,
};

View File

@ -1,24 +0,0 @@
From 8e34da603f442624bb70e887d8f42064bb924224 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 28 Jul 2013 18:03:54 +0200
Subject: [PATCH 13/36] MTD: lantiq: xway: fix invalid operator
xway_read_byte should use a logic or and not an add operator when working out
the nand address.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/nand/xway_nand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
@@ -124,7 +124,7 @@ static unsigned char xway_read_byte(stru
int ret;
spin_lock_irqsave(&ebu_lock, flags);
- ret = ltq_r8((void __iomem *)(nandaddr + NAND_READ_DATA));
+ ret = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
spin_unlock_irqrestore(&ebu_lock, flags);
return ret;

View File

@ -1,44 +0,0 @@
From b454cefd675fc1bd3d8c690c1bd1d8f4678e9922 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 28 Jul 2013 18:06:39 +0200
Subject: [PATCH 14/36] MTD: lantiq: xway: the latched command should be
persistent
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/nand/xway_nand.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
@@ -54,6 +54,8 @@
#define NAND_CON_CSMUX (1 << 1)
#define NAND_CON_NANDM 1
+static u32 xway_latchcmd;
+
static void xway_reset_chip(struct nand_chip *chip)
{
unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
@@ -94,17 +96,15 @@ static void xway_cmd_ctrl(struct mtd_inf
unsigned long flags;
if (ctrl & NAND_CTRL_CHANGE) {
- nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR);
if (ctrl & NAND_CLE)
- nandaddr |= NAND_WRITE_CMD;
- else
- nandaddr |= NAND_WRITE_ADDR;
- this->IO_ADDR_W = (void __iomem *) nandaddr;
+ xway_latchcmd = NAND_WRITE_CMD;
+ else if (ctrl & NAND_ALE)
+ xway_latchcmd = NAND_WRITE_ADDR;
}
if (cmd != NAND_CMD_NONE) {
spin_lock_irqsave(&ebu_lock, flags);
- writeb(cmd, this->IO_ADDR_W);
+ writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd));
while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
;
spin_unlock_irqrestore(&ebu_lock, flags);

View File

@ -1,41 +0,0 @@
From 76e153079f02d26e3357302d2886a0c8aaaec64d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 28 Jul 2013 18:02:06 +0200
Subject: [PATCH 15/36] MTD: lantiq: xway: remove endless loop
The reset loop logic could run into a endless loop. Lets fix it as requested.
--> http://lists.infradead.org/pipermail/linux-mtd/2012-September/044240.html
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/nand/xway_nand.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
@@ -59,16 +59,22 @@ static u32 xway_latchcmd;
static void xway_reset_chip(struct nand_chip *chip)
{
unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
+ unsigned long timeout;
unsigned long flags;
nandaddr &= ~NAND_WRITE_ADDR;
nandaddr |= NAND_WRITE_CMD;
/* finish with a reset */
+ timeout = jiffies + msecs_to_jiffies(20);
+
spin_lock_irqsave(&ebu_lock, flags);
writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
- while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
- ;
+ do {
+ if ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+ break;
+ cond_resched();
+ } while (!time_after_eq(jiffies, timeout));
spin_unlock_irqrestore(&ebu_lock, flags);
}

View File

@ -1,55 +0,0 @@
From 65df9d63eaee02c25e879b33dd42aceb78e57842 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 28 Jul 2013 17:59:51 +0200
Subject: [PATCH 16/36] MTD: lantiq: xway: add missing write_buf and read_buf
to nand driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/nand/xway_nand.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
@@ -136,6 +136,32 @@ static unsigned char xway_read_byte(stru
return ret;
}
+static void xway_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ struct nand_chip *this = mtd->priv;
+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
+ unsigned long flags;
+ int i;
+
+ spin_lock_irqsave(&ebu_lock, flags);
+ for (i = 0; i < len; i++)
+ buf[i] = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
+ spin_unlock_irqrestore(&ebu_lock, flags);
+}
+
+static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ struct nand_chip *this = mtd->priv;
+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
+ unsigned long flags;
+ int i;
+
+ spin_lock_irqsave(&ebu_lock, flags);
+ for (i = 0; i < len; i++)
+ ltq_w8(buf[i], (void __iomem *)(nandaddr | NAND_WRITE_DATA));
+ spin_unlock_irqrestore(&ebu_lock, flags);
+}
+
static int xway_nand_probe(struct platform_device *pdev)
{
struct nand_chip *this = platform_get_drvdata(pdev);
@@ -177,6 +203,8 @@ static struct platform_nand_data xway_na
.dev_ready = xway_dev_ready,
.select_chip = xway_select_chip,
.read_byte = xway_read_byte,
+ .read_buf = xway_read_buf,
+ .write_buf = xway_write_buf,
}
};

View File

@ -1,89 +0,0 @@
From aa705c1b0860da91f2ed1a4c0b57337e6de689e1 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Aug 2014 18:55:31 +0200
Subject: [PATCH 17/36] MTD: xway: fix nand locking
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/nand/xway_nand.c | 15 +++------------
1 file changed, 3 insertions(+), 12 deletions(-)
--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
@@ -80,13 +80,16 @@ static void xway_reset_chip(struct nand_
static void xway_select_chip(struct mtd_info *mtd, int chip)
{
+ static unsigned long csflags;
switch (chip) {
case -1:
ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
+ spin_unlock_irqrestore(&ebu_lock, csflags);
break;
case 0:
+ spin_lock_irqsave(&ebu_lock, csflags);
ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
break;
@@ -99,7 +102,6 @@ static void xway_cmd_ctrl(struct mtd_inf
{
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
- unsigned long flags;
if (ctrl & NAND_CTRL_CHANGE) {
if (ctrl & NAND_CLE)
@@ -109,11 +111,9 @@ static void xway_cmd_ctrl(struct mtd_inf
}
if (cmd != NAND_CMD_NONE) {
- spin_lock_irqsave(&ebu_lock, flags);
writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd));
while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
;
- spin_unlock_irqrestore(&ebu_lock, flags);
}
}
@@ -126,12 +126,9 @@ static unsigned char xway_read_byte(stru
{
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
- unsigned long flags;
int ret;
- spin_lock_irqsave(&ebu_lock, flags);
ret = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
- spin_unlock_irqrestore(&ebu_lock, flags);
return ret;
}
@@ -140,26 +137,20 @@ static void xway_read_buf(struct mtd_inf
{
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
- unsigned long flags;
int i;
- spin_lock_irqsave(&ebu_lock, flags);
for (i = 0; i < len; i++)
buf[i] = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
- spin_unlock_irqrestore(&ebu_lock, flags);
}
static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
- unsigned long flags;
int i;
- spin_lock_irqsave(&ebu_lock, flags);
for (i = 0; i < len; i++)
ltq_w8(buf[i], (void __iomem *)(nandaddr | NAND_WRITE_DATA));
- spin_unlock_irqrestore(&ebu_lock, flags);
}
static int xway_nand_probe(struct platform_device *pdev)

View File

@ -1,125 +0,0 @@
From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 9 Sep 2014 23:12:15 +0200
Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/nand/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
@@ -54,8 +54,27 @@
#define NAND_CON_CSMUX (1 << 1)
#define NAND_CON_NANDM 1
+#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr))
+#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400)
+#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080)
+
static u32 xway_latchcmd;
+/*
+ * req_mask provides a mechanism to prevent interference between
+ * nand and pci (probably only relevant for the BT Home Hub 2B).
+ * Setting it causes the corresponding pci req pins to be masked
+ * during nand access, and also moves ebu locking from the read/write
+ * functions to the chip select function to ensure that the whole
+ * operation runs with interrupts disabled.
+ * In addition it switches on some extra waiting in xway_cmd_ctrl().
+ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,
+ * which in turn seems to be necessary for the nor chip to be recognised
+ * reliably, on a board (Home Hub 2B again) which has both nor and nand.
+ */
+
+static __be32 req_mask = 0;
+
static void xway_reset_chip(struct nand_chip *chip)
{
unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
@@ -86,12 +105,24 @@ static void xway_select_chip(struct mtd_
case -1:
ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
+
+ if (req_mask) {
+ /* Unmask all external PCI request */
+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);
+ }
spin_unlock_irqrestore(&ebu_lock, csflags);
+
break;
case 0:
spin_lock_irqsave(&ebu_lock, csflags);
+ if (req_mask) {
+ /* Mask all external PCI request */
+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);
+ }
+
ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
+
break;
default:
BUG();
@@ -103,6 +134,12 @@ static void xway_cmd_ctrl(struct mtd_inf
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
+ if (req_mask) {
+ if (cmd != NAND_CMD_STATUS)
+ ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */
+ }
+
+
if (ctrl & NAND_CTRL_CHANGE) {
if (ctrl & NAND_CLE)
xway_latchcmd = NAND_WRITE_CMD;
@@ -115,6 +152,24 @@ static void xway_cmd_ctrl(struct mtd_inf
while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
;
}
+
+ if (req_mask) {
+ /*
+ * program and erase have their own busy handlers
+ * status and sequential in needs no delay
+ */
+ switch (cmd) {
+ case NAND_CMD_ERASE1:
+ case NAND_CMD_SEQIN:
+ case NAND_CMD_STATUS:
+ case NAND_CMD_READID:
+ return;
+ }
+
+ /* wait until command is processed */
+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
+ ;
+ }
}
static int xway_dev_ready(struct mtd_info *mtd)
@@ -157,6 +212,8 @@ static int xway_nand_probe(struct platfo
{
struct nand_chip *this = platform_get_drvdata(pdev);
unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
+ const __be32 *req_mask_ptr = of_get_property(pdev->dev.of_node,
+ "req-mask", NULL);
const __be32 *cs = of_get_property(pdev->dev.of_node,
"lantiq,cs", NULL);
u32 cs_flag = 0;
@@ -165,6 +222,12 @@ static int xway_nand_probe(struct platfo
if (cs && (*cs == 1))
cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
+ /*
+ * Load the PCI req lines to mask from the device tree. If the
+ * property is not present, setting req_mask to 0 disables masking.
+ */
+ req_mask = (req_mask_ptr ? *req_mask_ptr : 0);
+
/* setup the EBU to run in NAND mode on our base addr */
ltq_ebu_w32(CPHYSADDR(nandaddr)
| ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);

View File

@ -1,25 +0,0 @@
From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Aug 2014 18:18:00 +0200
Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/maps/lantiq-flash.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
@@ -138,7 +138,11 @@ ltq_mtd_probe(struct platform_device *pd
if (!ltq_mtd->map)
return -ENOMEM;
- ltq_mtd->map->phys = ltq_mtd->res->start;
+ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
+ ltq_mtd->map->phys = NO_XIP;
+ else
+ ltq_mtd->map->phys = ltq_mtd->res->start;
+ ltq_mtd->res->start;
ltq_mtd->map->size = resource_size(ltq_mtd->res);
ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res);
if (IS_ERR(ltq_mtd->map->virt))

View File

@ -1,44 +0,0 @@
From 4400e1f593ea40a51912128adb4f53d59e62cad8 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 10 Sep 2014 22:40:18 +0200
Subject: [PATCH 22/36] MTD: m25p80: allow loading mtd name from OF
In accordance with the physmap flash we should honour the linux,mtd-name
property when deciding what name the mtd device has.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/devices/m25p80.c | 6 ++++++
1 file changed, 6 insertions(+)
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -19,6 +19,7 @@
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/device.h>
+#include <linux/of.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
@@ -204,6 +205,10 @@ static int m25p_probe(struct spi_device
enum read_mode mode = SPI_NOR_NORMAL;
char *flash_name = NULL;
int ret;
+ const char __maybe_unused *of_mtd_name = NULL;
+
+ of_property_read_string(spi->dev.of_node,
+ "linux,mtd-name", &of_mtd_name);
data = dev_get_platdata(&spi->dev);
@@ -234,6 +239,8 @@ static int m25p_probe(struct spi_device
if (data && data->name)
nor->mtd.name = data->name;
+ else if (of_mtd_name)
+ nor->mtd.name = of_mtd_name;
/* For some (historical?) reason many platforms provide two different
* names in flash_platform_data: "name" and "type". Quite often name is

View File

@ -1,364 +0,0 @@
From 77e89d5a28be35058041c79e9874ab26f222c603 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 22 Oct 2012 09:26:24 +0200
Subject: [PATCH 24/36] NET: lantiq: adds PHY11G firmware blobs
Signed-off-by: John Crispin <blogic@openwrt.org>
---
firmware/Makefile | 4 +
firmware/lantiq/COPYING | 286 +++++++++++++++++++++++++++++++++++++++++++++++
firmware/lantiq/README | 45 ++++++++
3 files changed, 335 insertions(+)
create mode 100644 firmware/lantiq/COPYING
create mode 100644 firmware/lantiq/README
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -134,6 +134,10 @@ fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_P
fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw
fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw
fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin
+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy11g_a1x.bin
+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy11g_a2x.bin
+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy22f_a1x.bin
+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy22f_a2x.bin
fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin
fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-)
--- /dev/null
+++ b/firmware/lantiq/COPYING
@@ -0,0 +1,286 @@
+All firmware files are copyrighted by Lantiq Deutschland GmbH.
+The files have been extracted from header files found in Lantiq BSPs.
+If not stated otherwise all files are licensed under GPL.
+
+=======================================================================
+
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
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+Foundation's software and to any other program whose authors commit to
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+ END OF TERMS AND CONDITIONS
--- /dev/null
+++ b/firmware/lantiq/README
@@ -0,0 +1,45 @@
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# (C) Copyright 2007 - 2012
+# Lantiq Deutschland GmbH
+#
+# (C) Copyright 2012
+# Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
+#
+
+#
+# How to use
+#
+Configure kernel with:
+CONFIG_FW_LOADER=y
+CONFIG_EXTRA_FIRMWARE_DIR="FIRMWARE_DIR"
+CONFIG_EXTRA_FIRMWARE="FIRMWARE_FILES"
+
+where FIRMWARE_DIR should point to this git tree and FIRMWARE_FILES is a list
+of space separated files from list below.
+
+#
+# Firmware files
+#
+
+# GPHY core on Lantiq XWAY VR9 v1.1
+lantiq/vr9_phy11g_a1x.bin
+lantiq/vr9_phy22f_a1x.bin
+
+# GPHY core on Lantiq XWAY VR9 v1.2
+lantiq/vr9_phy11g_a2x.bin
+lantiq/vr9_phy22f_a2x.bin

View File

@ -1,53 +0,0 @@
From c6feeeb407a3b8a6597ae377ba4dd138e185e3dd Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 27 Jul 2014 09:38:50 +0100
Subject: [PATCH 26/36] NET: multi phy support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/net/phy/phy.c | 9 ++++++---
include/linux/phy.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -893,7 +893,8 @@ void phy_state_machine(struct work_struc
/* If the link is down, give up on negotiation for now */
if (!phydev->link) {
phydev->state = PHY_NOLINK;
- netif_carrier_off(phydev->attached_dev);
+ if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(phydev->attached_dev);
phydev->adjust_link(phydev->attached_dev);
break;
}
@@ -985,7 +986,8 @@ void phy_state_machine(struct work_struc
netif_carrier_on(phydev->attached_dev);
} else {
phydev->state = PHY_NOLINK;
- netif_carrier_off(phydev->attached_dev);
+ if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(phydev->attached_dev);
}
phydev->adjust_link(phydev->attached_dev);
@@ -997,7 +999,8 @@ void phy_state_machine(struct work_struc
case PHY_HALTED:
if (phydev->link) {
phydev->link = 0;
- netif_carrier_off(phydev->attached_dev);
+ if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(phydev->attached_dev);
phydev->adjust_link(phydev->attached_dev);
do_suspend = true;
}
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -377,6 +377,7 @@ struct phy_device {
bool is_pseudo_fixed_link;
bool has_fixups;
bool suspended;
+ bool no_auto_carrier_off;
enum phy_state state;

View File

@ -1,911 +0,0 @@
From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 9 Sep 2014 22:45:34 +0200
Subject: [PATCH 28/36] NET: lantiq: various etop fixes
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++-----------
1 file changed, 389 insertions(+), 166 deletions(-)
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -11,7 +11,7 @@
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*
- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
*/
#include <linux/kernel.h>
@@ -30,11 +30,16 @@
#include <linux/mm.h>
#include <linux/platform_device.h>
#include <linux/ethtool.h>
+#include <linux/if_vlan.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/of_net.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
#include <asm/checksum.h>
@@ -42,7 +47,7 @@
#include <xway_dma.h>
#include <lantiq_platform.h>
-#define LTQ_ETOP_MDIO 0x11804
+#define LTQ_ETOP_MDIO_ACC 0x11804
#define MDIO_REQUEST 0x80000000
#define MDIO_READ 0x40000000
#define MDIO_ADDR_MASK 0x1f
@@ -51,44 +56,91 @@
#define MDIO_REG_OFFSET 0x10
#define MDIO_VAL_MASK 0xffff
-#define PPE32_CGEN 0x800
-#define LQ_PPE32_ENET_MAC_CFG 0x1840
+#define LTQ_ETOP_MDIO_CFG 0x11800
+#define MDIO_CFG_MASK 0x6
+
+#define LTQ_ETOP_CFG 0x11808
+#define LTQ_ETOP_IGPLEN 0x11820
+#define LTQ_ETOP_MAC_CFG 0x11840
#define LTQ_ETOP_ENETS0 0x11850
#define LTQ_ETOP_MAC_DA0 0x1186C
#define LTQ_ETOP_MAC_DA1 0x11870
-#define LTQ_ETOP_CFG 0x16020
-#define LTQ_ETOP_IGPLEN 0x16080
+
+#define MAC_CFG_MASK 0xfff
+#define MAC_CFG_CGEN (1 << 11)
+#define MAC_CFG_DUPLEX (1 << 2)
+#define MAC_CFG_SPEED (1 << 1)
+#define MAC_CFG_LINK (1 << 0)
#define MAX_DMA_CHAN 0x8
#define MAX_DMA_CRC_LEN 0x4
#define MAX_DMA_DATA_LEN 0x600
#define ETOP_FTCU BIT(28)
-#define ETOP_MII_MASK 0xf
-#define ETOP_MII_NORMAL 0xd
-#define ETOP_MII_REVERSE 0xe
#define ETOP_PLEN_UNDER 0x40
-#define ETOP_CGEN 0x800
+#define ETOP_CFG_MII0 0x01
-/* use 2 static channels for TX/RX */
-#define LTQ_ETOP_TX_CHANNEL 1
-#define LTQ_ETOP_RX_CHANNEL 6
-#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
-#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
+#define ETOP_CFG_MASK 0xfff
+#define ETOP_CFG_FEN0 (1 << 8)
+#define ETOP_CFG_SEN0 (1 << 6)
+#define ETOP_CFG_OFF1 (1 << 3)
+#define ETOP_CFG_REMII0 (1 << 1)
+#define ETOP_CFG_OFF0 (1 << 0)
+
+#define LTQ_GBIT_MDIO_CTL 0xCC
+#define LTQ_GBIT_MDIO_DATA 0xd0
+#define LTQ_GBIT_GCTL0 0x68
+#define LTQ_GBIT_PMAC_HD_CTL 0x8c
+#define LTQ_GBIT_P0_CTL 0x4
+#define LTQ_GBIT_PMAC_RX_IPG 0xa8
+#define LTQ_GBIT_RGMII_CTL 0x78
+
+#define PMAC_HD_CTL_AS (1 << 19)
+#define PMAC_HD_CTL_RXSH (1 << 22)
+
+/* Switch Enable (0=disable, 1=enable) */
+#define GCTL0_SE 0x80000000
+/* Disable MDIO auto polling (0=disable, 1=enable) */
+#define PX_CTL_DMDIO 0x00400000
+
+/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
+#define MDC_CLOCK_MASK 0xff000000
+#define MDC_CLOCK_OFFSET 24
+
+/* register information for the gbit's MDIO bus */
+#define MDIO_XR9_REQUEST 0x00008000
+#define MDIO_XR9_READ 0x00000800
+#define MDIO_XR9_WRITE 0x00000400
+#define MDIO_XR9_REG_MASK 0x1f
+#define MDIO_XR9_ADDR_MASK 0x1f
+#define MDIO_XR9_RD_MASK 0xffff
+#define MDIO_XR9_REG_OFFSET 0
+#define MDIO_XR9_ADDR_OFFSET 5
+#define MDIO_XR9_WR_OFFSET 16
+#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \
+ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
+
+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
#define ltq_etop_w32_mask(x, y, z) \
ltq_w32_mask(x, y, ltq_etop_membase + (z))
-#define DRV_VERSION "1.0"
+#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
+#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
+#define ltq_gbit_w32_mask(x, y, z) \
+ ltq_w32_mask(x, y, ltq_gbit_membase + (z))
+
+#define DRV_VERSION "1.2"
static void __iomem *ltq_etop_membase;
+static void __iomem *ltq_gbit_membase;
struct ltq_etop_chan {
- int idx;
int tx_free;
+ int irq;
struct net_device *netdev;
struct napi_struct napi;
struct ltq_dma_channel dma;
@@ -98,22 +150,35 @@ struct ltq_etop_chan {
struct ltq_etop_priv {
struct net_device *netdev;
struct platform_device *pdev;
- struct ltq_eth_data *pldata;
struct resource *res;
struct mii_bus *mii_bus;
struct phy_device *phydev;
- struct ltq_etop_chan ch[MAX_DMA_CHAN];
- int tx_free[MAX_DMA_CHAN >> 1];
+ struct ltq_etop_chan txch;
+ struct ltq_etop_chan rxch;
+
+ int tx_irq;
+ int rx_irq;
+
+ unsigned char mac[6];
+ int mii_mode;
spinlock_t lock;
+
+ struct clk *clk_ppe;
+ struct clk *clk_switch;
+ struct clk *clk_ephy;
+ struct clk *clk_ephycgu;
};
+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
+ int phy_reg, u16 phy_data);
+
static int
ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
{
- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
+ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
if (!ch->skb[ch->dma.desc])
return -ENOMEM;
ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
@@ -148,8 +213,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
spin_unlock_irqrestore(&priv->lock, flags);
skb_put(skb, len);
+ skb->dev = ch->netdev;
skb->protocol = eth_type_trans(skb, ch->netdev);
netif_receive_skb(skb);
+ ch->netdev->stats.rx_packets++;
+ ch->netdev->stats.rx_bytes += len;
}
static int
@@ -157,8 +225,10 @@ ltq_etop_poll_rx(struct napi_struct *nap
{
struct ltq_etop_chan *ch = container_of(napi,
struct ltq_etop_chan, napi);
+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
int rx = 0;
int complete = 0;
+ unsigned long flags;
while ((rx < budget) && !complete) {
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
@@ -172,7 +242,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
}
if (complete || !rx) {
napi_complete(&ch->napi);
+ spin_lock_irqsave(&priv->lock, flags);
ltq_dma_ack_irq(&ch->dma);
+ spin_unlock_irqrestore(&priv->lock, flags);
}
return rx;
}
@@ -184,12 +256,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
container_of(napi, struct ltq_etop_chan, napi);
struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
struct netdev_queue *txq =
- netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
+ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
while ((ch->dma.desc_base[ch->tx_free].ctl &
(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
+ ch->netdev->stats.tx_packets++;
+ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
dev_kfree_skb_any(ch->skb[ch->tx_free]);
ch->skb[ch->tx_free] = NULL;
memset(&ch->dma.desc_base[ch->tx_free], 0,
@@ -202,7 +276,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
if (netif_tx_queue_stopped(txq))
netif_tx_start_queue(txq);
napi_complete(&ch->napi);
+ spin_lock_irqsave(&priv->lock, flags);
ltq_dma_ack_irq(&ch->dma);
+ spin_unlock_irqrestore(&priv->lock, flags);
return 1;
}
@@ -210,9 +286,10 @@ static irqreturn_t
ltq_etop_dma_irq(int irq, void *_priv)
{
struct ltq_etop_priv *priv = _priv;
- int ch = irq - LTQ_DMA_CH0_INT;
-
- napi_schedule(&priv->ch[ch].napi);
+ if (irq == priv->txch.dma.irq)
+ napi_schedule(&priv->txch.napi);
+ else
+ napi_schedule(&priv->rxch.napi);
return IRQ_HANDLED;
}
@@ -224,7 +301,7 @@ ltq_etop_free_channel(struct net_device
ltq_dma_free(&ch->dma);
if (ch->dma.irq)
free_irq(ch->dma.irq, priv);
- if (IS_RX(ch->idx)) {
+ if (ch == &priv->txch) {
int desc;
for (desc = 0; desc < LTQ_DESC_NUM; desc++)
dev_kfree_skb_any(ch->skb[ch->dma.desc]);
@@ -235,65 +312,133 @@ static void
ltq_etop_hw_exit(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- int i;
- ltq_pmu_disable(PMU_PPE);
- for (i = 0; i < MAX_DMA_CHAN; i++)
- if (IS_TX(i) || IS_RX(i))
- ltq_etop_free_channel(dev, &priv->ch[i]);
+ clk_disable(priv->clk_ppe);
+
+ if (of_machine_is_compatible("lantiq,ar9"))
+ clk_disable(priv->clk_switch);
+
+ if (of_machine_is_compatible("lantiq,ase")) {
+ clk_disable(priv->clk_ephy);
+ clk_disable(priv->clk_ephycgu);
+ }
+
+ ltq_etop_free_channel(dev, &priv->txch);
+ ltq_etop_free_channel(dev, &priv->rxch);
+}
+
+static void
+ltq_etop_gbit_init(struct net_device *dev)
+{
+ struct ltq_etop_priv *priv = netdev_priv(dev);
+
+ clk_enable(priv->clk_switch);
+
+ /* enable gbit port0 on the SoC */
+ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
+
+ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
+ /* disable MDIO auto polling mode */
+ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
+ /* set 1522 packet size */
+ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
+ /* disable pmac & dmac headers */
+ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
+ LTQ_GBIT_PMAC_HD_CTL);
+ /* Due to traffic halt when burst length 8,
+ replace default IPG value with 0x3B */
+ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
+ /* set mdc clock to 2.5 MHz */
+ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
+ LTQ_GBIT_RGMII_CTL);
}
static int
ltq_etop_hw_init(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- int i;
+ int mii_mode = priv->mii_mode;
- ltq_pmu_enable(PMU_PPE);
+ clk_enable(priv->clk_ppe);
+
+ if (of_machine_is_compatible("lantiq,ar9")) {
+ ltq_etop_gbit_init(dev);
+ /* force the etops link to the gbit to MII */
+ mii_mode = PHY_INTERFACE_MODE_MII;
+ }
+ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
+ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
+ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
- switch (priv->pldata->mii_mode) {
+ switch (mii_mode) {
case PHY_INTERFACE_MODE_RMII:
- ltq_etop_w32_mask(ETOP_MII_MASK,
- ETOP_MII_REVERSE, LTQ_ETOP_CFG);
+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
break;
case PHY_INTERFACE_MODE_MII:
- ltq_etop_w32_mask(ETOP_MII_MASK,
- ETOP_MII_NORMAL, LTQ_ETOP_CFG);
+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
break;
default:
+ if (of_machine_is_compatible("lantiq,ase")) {
+ clk_enable(priv->clk_ephy);
+ /* disable external MII */
+ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
+ /* enable clock for internal PHY */
+ clk_enable(priv->clk_ephycgu);
+ /* we need to write this magic to the internal phy to
+ make it work */
+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
+ pr_info("Selected EPHY mode\n");
+ break;
+ }
netdev_err(dev, "unknown mii mode %d\n",
- priv->pldata->mii_mode);
+ mii_mode);
return -ENOTSUPP;
}
- /* enable crc generation */
- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
+ return 0;
+}
+
+static int
+ltq_etop_dma_init(struct net_device *dev)
+{
+ struct ltq_etop_priv *priv = netdev_priv(dev);
+ int tx = priv->tx_irq - LTQ_DMA_ETOP;
+ int rx = priv->rx_irq - LTQ_DMA_ETOP;
+ int err;
ltq_dma_init_port(DMA_PORT_ETOP);
- for (i = 0; i < MAX_DMA_CHAN; i++) {
- int irq = LTQ_DMA_CH0_INT + i;
- struct ltq_etop_chan *ch = &priv->ch[i];
-
- ch->idx = ch->dma.nr = i;
-
- if (IS_TX(i)) {
- ltq_dma_alloc_tx(&ch->dma);
- request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
- } else if (IS_RX(i)) {
- ltq_dma_alloc_rx(&ch->dma);
- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
- ch->dma.desc++)
- if (ltq_etop_alloc_skb(ch))
- return -ENOMEM;
- ch->dma.desc = 0;
- request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
+ priv->txch.dma.nr = tx;
+ ltq_dma_alloc_tx(&priv->txch.dma);
+ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
+ if (err) {
+ netdev_err(dev, "failed to allocate tx irq\n");
+ goto err_out;
+ }
+ priv->txch.dma.irq = priv->tx_irq;
+
+ priv->rxch.dma.nr = rx;
+ ltq_dma_alloc_rx(&priv->rxch.dma);
+ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
+ priv->rxch.dma.desc++) {
+ if (ltq_etop_alloc_skb(&priv->rxch)) {
+ netdev_err(dev, "failed to allocate skbs\n");
+ err = -ENOMEM;
+ goto err_out;
}
- ch->dma.irq = irq;
}
- return 0;
+ priv->rxch.dma.desc = 0;
+ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
+ if (err)
+ netdev_err(dev, "failed to allocate rx irq\n");
+ else
+ priv->rxch.dma.irq = priv->rx_irq;
+err_out:
+ return err;
}
static void
@@ -309,7 +454,10 @@ ltq_etop_get_settings(struct net_device
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- return phy_ethtool_gset(priv->phydev, cmd);
+ if (priv->phydev)
+ return phy_ethtool_gset(priv->phydev, cmd);
+ else
+ return 0;
}
static int
@@ -317,7 +465,10 @@ ltq_etop_set_settings(struct net_device
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- return phy_ethtool_sset(priv->phydev, cmd);
+ if (priv->phydev)
+ return phy_ethtool_sset(priv->phydev, cmd);
+ else
+ return 0;
}
static int
@@ -325,7 +476,10 @@ ltq_etop_nway_reset(struct net_device *d
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- return phy_start_aneg(priv->phydev);
+ if (priv->phydev)
+ return phy_start_aneg(priv->phydev);
+ else
+ return 0;
}
static const struct ethtool_ops ltq_etop_ethtool_ops = {
@@ -336,6 +490,39 @@ static const struct ethtool_ops ltq_etop
};
static int
+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
+ int phy_reg, u16 phy_data)
+{
+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
+ (phy_data << MDIO_XR9_WR_OFFSET) |
+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
+
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
+ ;
+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
+ ;
+ return 0;
+}
+
+static int
+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
+{
+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
+
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
+ ;
+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
+ ;
+ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
+ return val;
+}
+
+static int
ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
{
u32 val = MDIO_REQUEST |
@@ -343,9 +530,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
phy_data;
- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
;
- ltq_etop_w32(val, LTQ_ETOP_MDIO);
+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
return 0;
}
@@ -356,12 +543,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
;
- ltq_etop_w32(val, LTQ_ETOP_MDIO);
- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
;
- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
+ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
return val;
}
@@ -376,14 +563,18 @@ ltq_etop_mdio_probe(struct net_device *d
{
struct ltq_etop_priv *priv = netdev_priv(dev);
struct phy_device *phydev = NULL;
- int phy_addr;
+ u32 phy_supported = (SUPPORTED_10baseT_Half
+ | SUPPORTED_10baseT_Full
+ | SUPPORTED_100baseT_Half
+ | SUPPORTED_100baseT_Full
+ | SUPPORTED_Autoneg
+ | SUPPORTED_MII
+ | SUPPORTED_TP);
- for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
- if (priv->mii_bus->phy_map[phy_addr]) {
- phydev = priv->mii_bus->phy_map[phy_addr];
- break;
- }
- }
+ if (of_machine_is_compatible("lantiq,ase"))
+ phydev = priv->mii_bus->phy_map[8];
+ else
+ phydev = priv->mii_bus->phy_map[0];
if (!phydev) {
netdev_err(dev, "no PHY found\n");
@@ -391,21 +582,18 @@ ltq_etop_mdio_probe(struct net_device *d
}
phydev = phy_connect(dev, dev_name(&phydev->dev),
- &ltq_etop_mdio_link, priv->pldata->mii_mode);
+ &ltq_etop_mdio_link, priv->mii_mode);
if (IS_ERR(phydev)) {
netdev_err(dev, "Could not attach to PHY\n");
return PTR_ERR(phydev);
}
- phydev->supported &= (SUPPORTED_10baseT_Half
- | SUPPORTED_10baseT_Full
- | SUPPORTED_100baseT_Half
- | SUPPORTED_100baseT_Full
- | SUPPORTED_Autoneg
- | SUPPORTED_MII
- | SUPPORTED_TP);
+ if (of_machine_is_compatible("lantiq,ar9"))
+ phy_supported |= SUPPORTED_1000baseT_Half
+ | SUPPORTED_1000baseT_Full;
+ phydev->supported &= phy_supported;
phydev->advertising = phydev->supported;
priv->phydev = phydev;
pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
@@ -430,8 +618,13 @@ ltq_etop_mdio_init(struct net_device *de
}
priv->mii_bus->priv = dev;
- priv->mii_bus->read = ltq_etop_mdio_rd;
- priv->mii_bus->write = ltq_etop_mdio_wr;
+ if (of_machine_is_compatible("lantiq,ar9")) {
+ priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
+ priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
+ } else {
+ priv->mii_bus->read = ltq_etop_mdio_rd;
+ priv->mii_bus->write = ltq_etop_mdio_wr;
+ }
priv->mii_bus->name = "ltq_mii";
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
priv->pdev->name, priv->pdev->id);
@@ -480,17 +673,19 @@ static int
ltq_etop_open(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- int i;
+ unsigned long flags;
- for (i = 0; i < MAX_DMA_CHAN; i++) {
- struct ltq_etop_chan *ch = &priv->ch[i];
+ napi_enable(&priv->txch.napi);
+ napi_enable(&priv->rxch.napi);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ ltq_dma_open(&priv->txch.dma);
+ ltq_dma_open(&priv->rxch.dma);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ if (priv->phydev)
+ phy_start(priv->phydev);
- if (!IS_TX(i) && (!IS_RX(i)))
- continue;
- ltq_dma_open(&ch->dma);
- napi_enable(&ch->napi);
- }
- phy_start(priv->phydev);
netif_tx_start_all_queues(dev);
return 0;
}
@@ -499,18 +694,19 @@ static int
ltq_etop_stop(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- int i;
+ unsigned long flags;
netif_tx_stop_all_queues(dev);
- phy_stop(priv->phydev);
- for (i = 0; i < MAX_DMA_CHAN; i++) {
- struct ltq_etop_chan *ch = &priv->ch[i];
-
- if (!IS_RX(i) && !IS_TX(i))
- continue;
- napi_disable(&ch->napi);
- ltq_dma_close(&ch->dma);
- }
+ if (priv->phydev)
+ phy_stop(priv->phydev);
+ napi_disable(&priv->txch.napi);
+ napi_disable(&priv->rxch.napi);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ ltq_dma_close(&priv->txch.dma);
+ ltq_dma_close(&priv->rxch.dma);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
return 0;
}
@@ -520,16 +716,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
int queue = skb_get_queue_mapping(skb);
struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
struct ltq_etop_priv *priv = netdev_priv(dev);
- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
- int len;
+ struct ltq_dma_desc *desc =
+ &priv->txch.dma.desc_base[priv->txch.dma.desc];
unsigned long flags;
u32 byte_offset;
+ int len;
len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
- dev_kfree_skb_any(skb);
+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
+ priv->txch.skb[priv->txch.dma.desc]) {
netdev_err(dev, "tx ring full\n");
netif_tx_stop_queue(txq);
return NETDEV_TX_BUSY;
@@ -537,7 +733,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
/* dma needs to start on a 16 byte aligned address */
byte_offset = CPHYSADDR(skb->data) % 16;
- ch->skb[ch->dma.desc] = skb;
+ priv->txch.skb[priv->txch.dma.desc] = skb;
dev->trans_start = jiffies;
@@ -547,11 +743,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
wmb();
desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
- ch->dma.desc++;
- ch->dma.desc %= LTQ_DESC_NUM;
+ priv->txch.dma.desc++;
+ priv->txch.dma.desc %= LTQ_DESC_NUM;
spin_unlock_irqrestore(&priv->lock, flags);
- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
+ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
netif_tx_stop_queue(txq);
return NETDEV_TX_OK;
@@ -566,8 +762,10 @@ ltq_etop_change_mtu(struct net_device *d
struct ltq_etop_priv *priv = netdev_priv(dev);
unsigned long flags;
+ int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
+
spin_lock_irqsave(&priv->lock, flags);
- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
+ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max,
LTQ_ETOP_IGPLEN);
spin_unlock_irqrestore(&priv->lock, flags);
}
@@ -638,6 +836,9 @@ ltq_etop_init(struct net_device *dev)
if (err)
goto err_hw;
ltq_etop_change_mtu(dev, 1500);
+ err = ltq_etop_dma_init(dev);
+ if (err)
+ goto err_hw;
memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
if (!is_valid_ether_addr(mac.sa_data)) {
@@ -655,9 +856,10 @@ ltq_etop_init(struct net_device *dev)
dev->addr_assign_type = NET_ADDR_RANDOM;
ltq_etop_set_multicast_list(dev);
- err = ltq_etop_mdio_init(dev);
- if (err)
- goto err_netdev;
+ if (!ltq_etop_mdio_init(dev))
+ dev->ethtool_ops = &ltq_etop_ethtool_ops;
+ else
+ pr_warn("etop: mdio probe failed\n");;
return 0;
err_netdev:
@@ -677,6 +879,9 @@ ltq_etop_tx_timeout(struct net_device *d
err = ltq_etop_hw_init(dev);
if (err)
goto err_hw;
+ err = ltq_etop_dma_init(dev);
+ if (err)
+ goto err_hw;
dev->trans_start = jiffies;
netif_wake_queue(dev);
return;
@@ -700,14 +905,19 @@ static const struct net_device_ops ltq_e
.ndo_tx_timeout = ltq_etop_tx_timeout,
};
-static int __init
-ltq_etop_probe(struct platform_device *pdev)
+static int ltq_etop_probe(struct platform_device *pdev)
{
struct net_device *dev;
struct ltq_etop_priv *priv;
- struct resource *res;
+ struct resource *res, *gbit_res, irqres[2];
+ const u8 *mac;
int err;
- int i;
+
+ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
+ if (err != 2) {
+ dev_err(&pdev->dev, "failed to get etop irqs\n");
+ return -EINVAL;
+ }
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -733,30 +943,61 @@ ltq_etop_probe(struct platform_device *p
goto err_out;
}
- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
- if (!dev) {
- err = -ENOMEM;
- goto err_out;
+ if (of_machine_is_compatible("lantiq,ar9")) {
+ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!gbit_res) {
+ dev_err(&pdev->dev, "failed to get gbit resource\n");
+ err = -ENOENT;
+ goto err_out;
+ }
+ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
+ gbit_res->start, resource_size(gbit_res));
+ if (!ltq_gbit_membase) {
+ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
+ pdev->id);
+ err = -ENOMEM;
+ goto err_out;
+ }
}
+
+ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
strcpy(dev->name, "eth%d");
dev->netdev_ops = &ltq_eth_netdev_ops;
- dev->ethtool_ops = &ltq_etop_ethtool_ops;
priv = netdev_priv(dev);
priv->res = res;
priv->pdev = pdev;
- priv->pldata = dev_get_platdata(&pdev->dev);
priv->netdev = dev;
+ priv->tx_irq = irqres[0].start;
+ priv->rx_irq = irqres[1].start;
+ priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
+
+ mac = of_get_mac_address(pdev->dev.of_node);
+ if (mac)
+ memcpy(priv->mac, mac, ETH_ALEN);
+
+ priv->clk_ppe = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(priv->clk_ppe))
+ return PTR_ERR(priv->clk_ppe);
+ if (of_machine_is_compatible("lantiq,ar9")) {
+ priv->clk_switch = clk_get(&pdev->dev, "switch");
+ if (IS_ERR(priv->clk_switch))
+ return PTR_ERR(priv->clk_switch);
+ }
+ if (of_machine_is_compatible("lantiq,ase")) {
+ priv->clk_ephy = clk_get(&pdev->dev, "ephy");
+ if (IS_ERR(priv->clk_ephy))
+ return PTR_ERR(priv->clk_ephy);
+ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
+ if (IS_ERR(priv->clk_ephycgu))
+ return PTR_ERR(priv->clk_ephycgu);
+ }
+
spin_lock_init(&priv->lock);
- for (i = 0; i < MAX_DMA_CHAN; i++) {
- if (IS_TX(i))
- netif_napi_add(dev, &priv->ch[i].napi,
- ltq_etop_poll_tx, 8);
- else if (IS_RX(i))
- netif_napi_add(dev, &priv->ch[i].napi,
- ltq_etop_poll_rx, 32);
- priv->ch[i].netdev = dev;
- }
+ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
+ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
+ priv->txch.netdev = dev;
+ priv->rxch.netdev = dev;
err = register_netdev(dev);
if (err)
@@ -785,31 +1026,22 @@ ltq_etop_remove(struct platform_device *
return 0;
}
+static const struct of_device_id ltq_etop_match[] = {
+ { .compatible = "lantiq,etop-xway" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ltq_etop_match);
+
static struct platform_driver ltq_mii_driver = {
+ .probe = ltq_etop_probe,
.remove = ltq_etop_remove,
.driver = {
.name = "ltq_etop",
+ .of_match_table = ltq_etop_match,
},
};
-int __init
-init_ltq_etop(void)
-{
- int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
-
- if (ret)
- pr_err("ltq_etop: Error registering platform driver!");
- return ret;
-}
-
-static void __exit
-exit_ltq_etop(void)
-{
- platform_driver_unregister(&ltq_mii_driver);
-}
-
-module_init(init_ltq_etop);
-module_exit(exit_ltq_etop);
+module_platform_driver(ltq_mii_driver);
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION("Lantiq SoC ETOP");

View File

@ -1,170 +0,0 @@
From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 12 Aug 2014 20:49:27 +0200
Subject: [PATCH 30/36] GPIO: add named gpio exports
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++
drivers/gpio/gpiolib.c | 11 +++++--
include/asm-generic/gpio.h | 5 +++
include/linux/gpio/consumer.h | 8 +++++
4 files changed, 90 insertions(+), 2 deletions(-)
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -23,6 +23,8 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/slab.h>
#include <linux/gpio/machine.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
#include "gpiolib.h"
@@ -450,3 +452,73 @@ void of_gpiochip_remove(struct gpio_chip
gpiochip_remove_pin_ranges(chip);
of_node_put(chip->of_node);
}
+
+#ifdef CONFIG_GPIO_SYSFS
+
+static struct of_device_id gpio_export_ids[] = {
+ { .compatible = "gpio-export" },
+ { /* sentinel */ }
+};
+
+static int __init of_gpio_export_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *cnp;
+ u32 val;
+ int nb = 0;
+
+ for_each_child_of_node(np, cnp) {
+ const char *name = NULL;
+ int gpio;
+ bool dmc;
+ int max_gpio = 1;
+ int i;
+
+ of_property_read_string(cnp, "gpio-export,name", &name);
+
+ if (!name)
+ max_gpio = of_gpio_count(cnp);
+
+ for (i = 0; i < max_gpio; i++) {
+ unsigned flags = 0;
+ enum of_gpio_flags of_flags;
+
+ gpio = of_get_gpio_flags(cnp, i, &of_flags);
+
+ if (of_flags == OF_GPIO_ACTIVE_LOW)
+ flags |= GPIOF_ACTIVE_LOW;
+
+ if (!of_property_read_u32(cnp, "gpio-export,output", &val))
+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
+ else
+ flags |= GPIOF_IN;
+
+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
+ continue;
+
+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
+ gpio_export_with_name(gpio, dmc, name);
+ nb++;
+ }
+ }
+
+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
+
+ return 0;
+}
+
+static struct platform_driver gpio_export_driver = {
+ .driver = {
+ .name = "gpio-export",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(gpio_export_ids),
+ },
+};
+
+static int __init of_gpio_export_init(void)
+{
+ return platform_driver_probe(&gpio_export_driver, of_gpio_export_probe);
+}
+device_initcall(of_gpio_export_init);
+
+#endif
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -122,6 +122,12 @@ static inline int gpio_export(unsigned g
return gpiod_export(gpio_to_desc(gpio), direction_may_change);
}
+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
+{
+ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
+}
+
static inline int gpio_export_link(struct device *dev, const char *name,
unsigned gpio)
{
--- a/include/linux/gpio/consumer.h
+++ b/include/linux/gpio/consumer.h
@@ -427,6 +427,7 @@ static inline struct gpio_desc *devm_get
#if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
int gpiod_export_link(struct device *dev, const char *name,
struct gpio_desc *desc);
@@ -434,6 +435,13 @@ void gpiod_unexport(struct gpio_desc *de
#else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
+static inline int _gpiod_export(struct gpio_desc *desc,
+ bool direction_may_change,
+ const char *name)
+{
+ return -ENOSYS;
+}
+
static inline int gpiod_export(struct gpio_desc *desc,
bool direction_may_change)
{
--- a/drivers/gpio/gpiolib-sysfs.c
+++ b/drivers/gpio/gpiolib-sysfs.c
@@ -544,7 +544,7 @@ static struct class gpio_class = {
*
* Returns zero on success, else an error.
*/
-int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
{
struct gpio_chip *chip;
struct gpiod_data *data;
@@ -604,6 +604,8 @@ int gpiod_export(struct gpio_desc *desc,
offset = gpio_chip_hwgpio(desc);
if (chip->names && chip->names[offset])
ioname = chip->names[offset];
+ if (name)
+ ioname = name;
dev = device_create_with_groups(&gpio_class, chip->dev,
MKDEV(0, 0), data, gpio_groups,
@@ -625,6 +627,12 @@ err_unlock:
gpiod_dbg(desc, "%s: status %d\n", __func__, status);
return status;
}
+EXPORT_SYMBOL_GPL(__gpiod_export);
+
+int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
+{
+ return __gpiod_export(desc, direction_may_change, NULL);
+}
EXPORT_SYMBOL_GPL(gpiod_export);
static int match_export(struct device *dev, const void *desc)

View File

@ -1,219 +0,0 @@
From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 10 Sep 2014 22:42:14 +0200
Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling
Signed-off-by: John Crispin <blogic@openwrt.org>
---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +
arch/mips/lantiq/xway/Makefile | 3 +
arch/mips/lantiq/xway/ath5k_eep.c | 136 +++++++++++++++++++++
arch/mips/lantiq/xway/eth_mac.c | 25 ++++
drivers/net/ethernet/lantiq_etop.c | 6 +-
5 files changed, 172 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c
create mode 100644 arch/mips/lantiq/xway/eth_mac.c
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -104,5 +104,8 @@ int xrx200_gphy_boot(struct device *dev,
extern void ltq_pmu_enable(unsigned int module);
extern void ltq_pmu_disable(unsigned int module);
+/* allow the ethernet driver to load a flash mapped mac addr */
+const u8* ltq_get_eth_mac(void);
+
#endif /* CONFIG_SOC_TYPE_XWAY */
#endif /* _LTQ_XWAY_H__ */
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -8,4 +8,7 @@ endif
obj-y += vmmc.o
+obj-y += eth_mac.o
+obj-$(CONFIG_PCI) += ath5k_eep.o
+
obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
--- /dev/null
+++ b/arch/mips/lantiq/xway/ath5k_eep.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>
+ * Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2013 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
+ * Copyright (C) 2015 Vittorio Gambaletta <openwrt@vittgam.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/etherdevice.h>
+#include <linux/ath5k_platform.h>
+#include <linux/pci.h>
+#include <linux/err.h>
+#include <linux/mtd/mtd.h>
+#include <lantiq_soc.h>
+
+extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
+struct ath5k_platform_data ath5k_pdata;
+static u8 athxk_eeprom_mac[6];
+
+static int ath5k_pci_plat_dev_init(struct pci_dev *dev)
+{
+ dev->dev.platform_data = &ath5k_pdata;
+ return 0;
+}
+
+static int ath5k_eep_load;
+int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node, *mtd_np = NULL;
+ int mac_offset;
+ u32 mac_inc = 0;
+ int i;
+ struct mtd_info *the_mtd;
+ size_t flash_readlen;
+ const __be32 *list;
+ const char *part;
+ phandle phandle;
+
+ list = of_get_property(np, "ath,eep-flash", &i);
+ if (!list || (i != (2 * sizeof(*list))))
+ return -ENODEV;
+
+ phandle = be32_to_cpup(list++);
+ if (phandle)
+ mtd_np = of_find_node_by_phandle(phandle);
+
+ if (!mtd_np)
+ return -ENODEV;
+
+ part = of_get_property(mtd_np, "label", NULL);
+ if (!part)
+ part = mtd_np->name;
+
+ the_mtd = get_mtd_device_nm(part);
+ if (IS_ERR(the_mtd))
+ return -ENODEV;
+
+ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL);
+
+ i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1,
+ &flash_readlen, (void *) ath5k_pdata.eeprom_data);
+
+ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
+ size_t mac_readlen;
+ mtd_read(the_mtd, mac_offset, 6, &mac_readlen,
+ (void *) athxk_eeprom_mac);
+ }
+ put_mtd_device(the_mtd);
+
+ if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) {
+ dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
+ return -ENODEV;
+ }
+
+ if (of_find_property(np, "ath,eep-swap", NULL))
+ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++)
+ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]);
+
+ if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac())
+ ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac());
+
+ if (!is_valid_ether_addr(athxk_eeprom_mac)) {
+ dev_warn(&pdev->dev, "using random mac\n");
+ random_ether_addr(athxk_eeprom_mac);
+ }
+
+ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
+ athxk_eeprom_mac[5] += mac_inc;
+
+ ath5k_pdata.macaddr = athxk_eeprom_mac;
+ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;
+
+ dev_info(&pdev->dev, "loaded ath5k eeprom\n");
+
+ return 0;
+}
+
+static struct of_device_id ath5k_eeprom_ids[] = {
+ { .compatible = "ath5k,eeprom" },
+ { }
+};
+
+static struct platform_driver ath5k_eeprom_driver = {
+ .driver = {
+ .name = "ath5k,eeprom",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(ath5k_eeprom_ids),
+ },
+};
+
+static int __init of_ath5k_eeprom_init(void)
+{
+ int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
+
+ if (ret)
+ ath5k_eep_load = 1;
+
+ return ret;
+}
+
+static int __init of_ath5k_eeprom_init_late(void)
+{
+ if (!ath5k_eep_load)
+ return 0;
+
+ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
+}
+late_initcall(of_ath5k_eeprom_init_late);
+subsys_initcall(of_ath5k_eeprom_init);
--- /dev/null
+++ b/arch/mips/lantiq/xway/eth_mac.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/if_ether.h>
+
+static u8 eth_mac[6];
+static int eth_mac_set;
+
+const u8* ltq_get_eth_mac(void)
+{
+ return eth_mac;
+}
+
+static int __init setup_ethaddr(char *str)
+{
+ eth_mac_set = mac_pton(str, eth_mac);
+ return !eth_mac_set;
+}
+early_param("ethaddr", setup_ethaddr);
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -840,7 +840,11 @@ ltq_etop_init(struct net_device *dev)
if (err)
goto err_hw;
- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
+ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN);
+
+ if (priv->mac && !is_valid_ether_addr(mac.sa_data))
+ memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
+
if (!is_valid_ether_addr(mac.sa_data)) {
pr_warn("etop: invalid MAC, using random\n");
eth_random_addr(mac.sa_data);

View File

@ -1,35 +0,0 @@
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -42,6 +42,7 @@
#include <linux/dma-mapping.h>
#include <linux/of_device.h>
#include <linux/mutex.h>
+#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
#include <linux/platform_data/s3c-hsotg.h>
@@ -336,6 +337,7 @@ static int dwc2_driver_probe(struct plat
struct resource *res;
int retval;
int irq;
+ int gpio_count;
match = of_match_device(dwc2_of_match_table, &dev->dev);
if (match && match->data) {
@@ -352,6 +354,16 @@ static int dwc2_driver_probe(struct plat
defparams.dma_desc_enable = 0;
}
+ gpio_count = of_gpio_count(dev->dev.of_node);
+ while (gpio_count > 0) {
+ enum of_gpio_flags flags;
+ int gpio = of_get_gpio_flags(dev->dev.of_node, --gpio_count, &flags);
+ if (gpio_request(gpio, "usb"))
+ continue;
+ dev_info(&dev->dev, "requested GPIO %d\n", gpio);
+ gpio_direction_output(gpio, (flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
+ }
+
hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
if (!hsotg)
return -ENOMEM;

View File

@ -1,23 +0,0 @@
From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Fri, 3 Jun 2016 13:12:20 +0200
Subject: [PATCH] arch: mips: increase io_space_limit
this value comes from x86 and breaks some pci devices
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/include/asm/io.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -50,7 +50,7 @@
/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
-#define IO_SPACE_LIMIT 0xffff
+#define IO_SPACE_LIMIT 0xffffffff
/*
* On MIPS I/O ports are memory mapped, so we access them using normal

View File

@ -1,28 +0,0 @@
From 57b588c950b7e04e0f22393ad439299ba4fda9c3 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 26 Nov 2015 11:00:09 +0100
Subject: [PATCH] pinctrl/lantiq: Fix GPIO Setup of GPIO Port3
Some special handling of GPIO Port 3 is needed because of
some hardware thingofabob.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Martin Schiller <mschiller@tdt.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/pinctrl-xway.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -1570,6 +1570,10 @@ static int xway_gpio_dir_out(struct gpio
{
struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
+ if (PORT(pin) == PORT3)
+ gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin));
+ else
+ gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin));
gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
xway_gpio_set(chip, pin, val);

View File

@ -1,28 +0,0 @@
From c9f294ff6584782d20b4a766901a9cff7398bb20 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 4 Jan 2016 22:27:57 +0100
Subject: [PATCH] pinctrl: lantiq: 2 pins have the wrong mux list
The latest vendor SDK contained this patch.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/pinctrl-xway.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -160,10 +160,10 @@ static const struct ltq_mfp_pin xway_mfp
MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE),
MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
- MFP_XWAY(GPIO44, GPIO, NONE, SIN, GPHY),
+ MFP_XWAY(GPIO44, GPIO, MII, SIN, GPHY),
MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN),
MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN),
- MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN),
+ MFP_XWAY(GPIO47, GPIO, MII, GPHY, SIN),
MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),

View File

@ -1,78 +0,0 @@
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -67,7 +67,7 @@ int gic_present;
#endif
static int exin_avail;
-static struct resource ltq_eiu_irq[MAX_EIU];
+static u32 ltq_eiu_irq[MAX_EIU];
static void __iomem *ltq_icu_membase[MAX_IM];
static void __iomem *ltq_eiu_membase;
static struct irq_domain *ltq_domain;
@@ -76,7 +76,7 @@ static int ltq_perfcount_irq;
int ltq_eiu_get_irq(int exin)
{
if (exin < exin_avail)
- return ltq_eiu_irq[exin].start;
+ return ltq_eiu_irq[exin];
return -1;
}
@@ -128,7 +128,7 @@ static int ltq_eiu_settype(struct irq_da
int i;
for (i = 0; i < MAX_EIU; i++) {
- if (d->hwirq == ltq_eiu_irq[i].start) {
+ if (d->hwirq == ltq_eiu_irq[i]) {
int val = 0;
int edge = 0;
@@ -176,7 +176,7 @@ static unsigned int ltq_startup_eiu_irq(
ltq_enable_irq(d);
for (i = 0; i < MAX_EIU; i++) {
- if (d->hwirq == ltq_eiu_irq[i].start) {
+ if (d->hwirq == ltq_eiu_irq[i]) {
/* by default we are low level triggered */
ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
/* clear all pending */
@@ -198,7 +198,7 @@ static void ltq_shutdown_eiu_irq(struct
ltq_disable_irq(d);
for (i = 0; i < MAX_EIU; i++) {
- if (d->hwirq == ltq_eiu_irq[i].start) {
+ if (d->hwirq == ltq_eiu_irq[i]) {
/* disable */
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
LTQ_EIU_EXIN_INEN);
@@ -343,10 +343,10 @@ static int icu_map(struct irq_domain *d,
return 0;
for (i = 0; i < exin_avail; i++)
- if (hw == ltq_eiu_irq[i].start)
+ if (hw == ltq_eiu_irq[i])
chip = &ltq_eiu_type;
- irq_set_chip_and_handler(hw, chip, handle_level_irq);
+ irq_set_chip_and_handler(irq, chip, handle_level_irq);
return 0;
}
@@ -441,14 +441,14 @@ int __init icu_of_init(struct device_nod
eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
/* find out how many external irq sources we have */
- exin_avail = of_irq_count(eiu_node);
+ exin_avail = of_property_count_u32_elems(eiu_node, "lantiq,eiu-irqs");
if (exin_avail > MAX_EIU)
exin_avail = MAX_EIU;
- ret = of_irq_to_resource_table(eiu_node,
+ ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
ltq_eiu_irq, exin_avail);
- if (ret != exin_avail)
+ if (ret)
panic("failed to load external irq resources");
if (!request_mem_region(res.start, resource_size(&res),

View File

@ -1,27 +0,0 @@
--- a/drivers/mtd/nand/plat_nand.c
+++ b/drivers/mtd/nand/plat_nand.c
@@ -31,6 +31,7 @@ static int plat_nand_probe(struct platfo
{
struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev);
struct mtd_part_parser_data ppdata;
+ struct device_node *np = pdev->dev.of_node;
struct plat_nand_data *data;
struct resource *res;
const char **part_types;
@@ -58,6 +59,7 @@ static int plat_nand_probe(struct platfo
return PTR_ERR(data->io_base);
data->chip.priv = &data;
+ data->chip.flash_node = np;
data->mtd.priv = &data->chip;
data->mtd.dev.parent = &pdev->dev;
@@ -105,7 +107,7 @@ static int plat_nand_probe(struct platfo
part_types = pdata->chip.part_probe_types;
- ppdata.of_node = pdev->dev.of_node;
+ ppdata.of_node = np;
err = mtd_device_parse_register(&data->mtd, part_types, &ppdata,
pdata->chip.partitions,
pdata->chip.nr_partitions);

View File

@ -1,23 +0,0 @@
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -301,12 +301,6 @@ static void ltq_machine_halt(void)
unreachable();
}
-static void ltq_machine_power_off(void)
-{
- local_irq_disable();
- unreachable();
-}
-
static void ltq_usb_init(void)
{
/* Power for USB cores 1 & 2 */
@@ -379,7 +373,6 @@ static int __init mips_reboot_setup(void
_machine_restart = ltq_machine_restart;
_machine_halt = ltq_machine_halt;
- pm_power_off = ltq_machine_power_off;
return 0;
}

View File

@ -1,87 +0,0 @@
From: Felix Fietkau <nbd@nbd.name>
Date: Thu, 19 Jan 2017 12:14:44 +0100
Subject: [PATCH] MIPS: Lantiq: Fix cascaded IRQ setup
With the IRQ stack changes integrated, the XRX200 devices started
emitting a constant stream of kernel messages like this:
[ 565.415310] Spurious IRQ: CAUSE=0x1100c300
This appears to be caused by IP0 firing for some reason without being
handled. Fix this by setting up IP2-6 as a proper chained IRQ handler and
calling do_IRQ for all MIPS CPU interrupts.
Cc: john@phrozen.org
Cc: stable@vger.kernel.org
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -271,6 +271,11 @@ static void ltq_hw5_irqdispatch(void)
DEFINE_HWx_IRQDISPATCH(5)
#endif
+static void ltq_hw_irq_handler(struct irq_desc *desc)
+{
+ ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
+}
+
#ifdef CONFIG_MIPS_MT_SMP
void __init arch_init_ipiirq(int irq, struct irqaction *action)
{
@@ -315,23 +320,19 @@ static struct irqaction irq_call = {
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
- unsigned int i;
+ int irq;
- if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
- do_IRQ(MIPS_CPU_TIMER_IRQ);
- goto out;
- } else {
- for (i = 0; i < MAX_IM; i++) {
- if (pending & (CAUSEF_IP2 << i)) {
- ltq_hw_irqdispatch(i);
- goto out;
- }
- }
+ if (!pending) {
+ spurious_interrupt();
+ return;
}
- pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
-out:
- return;
+ pending >>= CAUSEB_IP;
+ while (pending) {
+ irq = fls(pending) - 1;
+ do_IRQ(MIPS_CPU_IRQ_BASE + irq);
+ pending &= ~BIT(irq);
+ }
}
static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
@@ -356,11 +357,6 @@ static const struct irq_domain_ops irq_d
.map = icu_map,
};
-static struct irqaction cascade = {
- .handler = no_action,
- .name = "cascade",
-};
-
int __init icu_of_init(struct device_node *node, struct device_node *parent)
{
struct device_node *eiu_node;
@@ -392,7 +388,7 @@ int __init icu_of_init(struct device_nod
mips_cpu_irq_init();
for (i = 0; i < MAX_IM; i++)
- setup_irq(i + 2, &cascade);
+ irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
if (cpu_has_vint) {
pr_info("Setting up vectored interrupts\n");

View File

@ -1,78 +0,0 @@
From 6c0c0951bbf8c2c216675fe277fba4c42aa0a2bf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Antti=20Sepp=C3=A4l=C3=A4?= <a.seppala@gmail.com>
Date: Sat, 27 Feb 2016 12:31:24 +0200
Subject: [PATCH] usb: dwc2: Add support for Lantiq ARX and XRX SoCs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add support for Lantiq ARX and XRX SoC families to the dwc2 driver.
Acked-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
---
Documentation/devicetree/bindings/usb/dwc2.txt | 2 ++
drivers/usb/dwc2/platform.c | 34 ++++++++++++++++++++++++++
2 files changed, 36 insertions(+)
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -7,6 +7,8 @@ Required properties:
- rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
- "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
- "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
+ - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
+ - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
- snps,dwc2: A generic DWC2 USB controller with default parameters.
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -116,6 +116,37 @@ static const struct dwc2_core_params par
.hibernation = -1,
};
+static const struct dwc2_core_params params_ltq = {
+ .otg_cap = 2, /* non-HNP/non-SRP */
+ .otg_ver = -1,
+ .dma_enable = -1,
+ .dma_desc_enable = -1,
+ .speed = -1,
+ .enable_dynamic_fifo = -1,
+ .en_multiple_tx_fifo = -1,
+ .host_rx_fifo_size = 288, /* 288 DWORDs */
+ .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
+ .host_perio_tx_fifo_size = 96, /* 96 DWORDs */
+ .max_transfer_size = 65535,
+ .max_packet_count = 511,
+ .host_channels = -1,
+ .phy_type = -1,
+ .phy_utmi_width = -1,
+ .phy_ulpi_ddr = -1,
+ .phy_ulpi_ext_vbus = -1,
+ .i2c_enable = -1,
+ .ulpi_fs_ls = -1,
+ .host_support_fs_ls_low_power = -1,
+ .host_ls_low_power_phy_clk = -1,
+ .ts_dline = -1,
+ .reload_ctl = -1,
+ .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
+ GAHBCFG_HBSTLEN_SHIFT,
+ .uframe_sched = -1,
+ .external_id_pin_ctl = -1,
+ .hibernation = -1,
+};
+
static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
{
struct platform_device *pdev = to_platform_device(hsotg->dev);
@@ -310,6 +341,8 @@ static int dwc2_driver_remove(struct pla
static const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
{ .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
+ { .compatible = "lantiq,arx100-usb", .data = &params_ltq },
+ { .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
{ .compatible = "snps,dwc2", .data = NULL },
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
{},

View File

@ -1,129 +0,0 @@
From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Fri, 6 Jan 2017 17:55:24 +0100
Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs
The size of the internal RAM of the DesignWare USB controller changed
between the different Lantiq SoCs. We have the following sizes:
Amazon + Danube: 8 KByte
Amazon SE + arx100: 2 KByte
xrx200 + xrx300: 2.5 KByte
For Danube SoC we do not provide the params and let the driver decide
to use sane defaults, for the Amazon SE and arx100 we use small fifos
and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo.
The auto detection of max_transfer_size and max_packet_count should
work, so remove it.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++-------
1 file changed, 39 insertions(+), 7 deletions(-)
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -116,7 +116,37 @@ static const struct dwc2_core_params par
.hibernation = -1,
};
-static const struct dwc2_core_params params_ltq = {
+static const struct dwc2_core_params params_danube = {
+ .otg_cap = 2, /* non-HNP/non-SRP */
+ .otg_ver = -1,
+ .dma_enable = -1,
+ .dma_desc_enable = -1,
+ .speed = -1,
+ .enable_dynamic_fifo = -1,
+ .en_multiple_tx_fifo = -1,
+ .host_rx_fifo_size = -1,
+ .host_nperio_tx_fifo_size = -1,
+ .host_perio_tx_fifo_size = -1,
+ .max_transfer_size = -1,
+ .max_packet_count = -1,
+ .host_channels = -1,
+ .phy_type = -1,
+ .phy_utmi_width = -1,
+ .phy_ulpi_ddr = -1,
+ .phy_ulpi_ext_vbus = -1,
+ .i2c_enable = -1,
+ .ulpi_fs_ls = -1,
+ .host_support_fs_ls_low_power = -1,
+ .host_ls_low_power_phy_clk = -1,
+ .ts_dline = -1,
+ .reload_ctl = -1,
+ .ahbcfg = -1,
+ .uframe_sched = -1,
+ .external_id_pin_ctl = -1,
+ .hibernation = -1,
+};
+
+static const struct dwc2_core_params params_ase = {
.otg_cap = 2, /* non-HNP/non-SRP */
.otg_ver = -1,
.dma_enable = -1,
@@ -127,8 +157,38 @@ static const struct dwc2_core_params par
.host_rx_fifo_size = 288, /* 288 DWORDs */
.host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
.host_perio_tx_fifo_size = 96, /* 96 DWORDs */
- .max_transfer_size = 65535,
- .max_packet_count = 511,
+ .max_transfer_size = -1,
+ .max_packet_count = -1,
+ .host_channels = -1,
+ .phy_type = -1,
+ .phy_utmi_width = -1,
+ .phy_ulpi_ddr = -1,
+ .phy_ulpi_ext_vbus = -1,
+ .i2c_enable = -1,
+ .ulpi_fs_ls = -1,
+ .host_support_fs_ls_low_power = -1,
+ .host_ls_low_power_phy_clk = -1,
+ .ts_dline = -1,
+ .reload_ctl = -1,
+ .ahbcfg = -1,
+ .uframe_sched = -1,
+ .external_id_pin_ctl = -1,
+ .hibernation = -1,
+};
+
+static const struct dwc2_core_params params_xrx200 = {
+ .otg_cap = 2, /* non-HNP/non-SRP */
+ .otg_ver = -1,
+ .dma_enable = -1,
+ .dma_desc_enable = -1,
+ .speed = -1,
+ .enable_dynamic_fifo = -1,
+ .en_multiple_tx_fifo = -1,
+ .host_rx_fifo_size = 288, /* 288 DWORDs */
+ .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
+ .host_perio_tx_fifo_size = 136, /* 136 DWORDs */
+ .max_transfer_size = -1,
+ .max_packet_count = -1,
.host_channels = -1,
.phy_type = -1,
.phy_utmi_width = -1,
@@ -140,8 +200,7 @@ static const struct dwc2_core_params par
.host_ls_low_power_phy_clk = -1,
.ts_dline = -1,
.reload_ctl = -1,
- .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
- GAHBCFG_HBSTLEN_SHIFT,
+ .ahbcfg = -1,
.uframe_sched = -1,
.external_id_pin_ctl = -1,
.hibernation = -1,
@@ -341,8 +400,11 @@ static int dwc2_driver_remove(struct pla
static const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
{ .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
- { .compatible = "lantiq,arx100-usb", .data = &params_ltq },
- { .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
+ { .compatible = "lantiq,danube-usb", .data = &params_danube },
+ { .compatible = "lantiq,ase-usb", .data = &params_ase },
+ { .compatible = "lantiq,arx100-usb", .data = &params_ase },
+ { .compatible = "lantiq,xrx200-usb", .data = &params_xrx200 },
+ { .compatible = "lantiq,xrx300-usb", .data = &params_xrx200 },
{ .compatible = "snps,dwc2", .data = NULL },
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
{},

View File

@ -1,202 +0,0 @@
From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Fri, 6 Jan 2017 17:40:12 +0100
Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
This adds code to initialize the USB controller and PHY also on Danube,
Amazon SE and AR10. This code is based on the Vendor driver from
different UGW versions and compared to the hardware documentation.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/mips/lantiq/xway/reset.c | 120 ++++++++++++++++++++++++++++++----------
arch/mips/lantiq/xway/sysctrl.c | 20 +++++++
2 files changed, 110 insertions(+), 30 deletions(-)
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -72,6 +72,8 @@
#define RCU_USBCFG_HDSEL_BIT BIT(11)
#define RCU_USBCFG_HOST_END_BIT BIT(10)
#define RCU_USBCFG_SLV_END_BIT BIT(9)
+#define RCU_USBCFG_SLV_END_BIT_AR9 BIT(17)
+
/* USB reset bits */
#define RCU_USBRESET 0x0010
@@ -85,6 +87,8 @@
#define RCU_CFG1A 0x0038
#define RCU_CFG1B 0x003C
+#define RCU_CFG1_TX_PEE BIT(0)
+#define RCU_CFG1_DIS_THR_SHIFT 15 /* Disconnect Threshold */
/* USB PMU devices */
#define PMU_AHBM BIT(15)
@@ -306,38 +310,91 @@ static void ltq_usb_init(void)
/* Power for USB cores 1 & 2 */
ltq_pmu_enable(PMU_AHBM);
ltq_pmu_enable(PMU_USB0);
- ltq_pmu_enable(PMU_USB1);
- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
+ if (of_machine_is_compatible("lantiq,ar10") ||
+ of_machine_is_compatible("lantiq,grx390") ||
+ of_machine_is_compatible("lantiq,ar9") ||
+ of_machine_is_compatible("lantiq,vr9"))
+ ltq_pmu_enable(PMU_USB1);
+
+ if (of_machine_is_compatible("lantiq,vr9") ||
+ of_machine_is_compatible("lantiq,ar10")) {
+ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | RCU_CFG1_TX_PEE |
+ 7 << RCU_CFG1_DIS_THR_SHIFT, RCU_CFG1A);
+ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | RCU_CFG1_TX_PEE |
+ 7 << RCU_CFG1_DIS_THR_SHIFT, RCU_CFG1B);
+ }
/* Enable USB PHY power for cores 1 & 2 */
ltq_pmu_enable(PMU_USB0_P);
- ltq_pmu_enable(PMU_USB1_P);
+ if (of_machine_is_compatible("lantiq,ar10") ||
+ of_machine_is_compatible("lantiq,grx390") ||
+ of_machine_is_compatible("lantiq,ar9") ||
+ of_machine_is_compatible("lantiq,vr9"))
+ ltq_pmu_enable(PMU_USB1_P);
+
+ if (of_machine_is_compatible("lantiq,ase") ||
+ of_machine_is_compatible("lantiq,danube")) {
+ /* Configure cores to host mode */
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
+ RCU_USB1CFG);
+
+ /* Select DMA endianness (Host-endian: big-endian) */
+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
+ }
+
+ if (of_machine_is_compatible("lantiq,ar9")) {
+ /* Configure cores to host mode */
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
+ RCU_USB1CFG);
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
+ RCU_USB2CFG);
+
+ /* Select DMA endianness (Host-endian: big-endian) */
+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT_AR9)
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
+ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT_AR9)
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
+ }
+
+ if (of_machine_is_compatible("lantiq,vr9") ||
+ of_machine_is_compatible("lantiq,ar10")) {
+ /* Configure cores to host mode */
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
+ RCU_USB1CFG);
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
+ RCU_USB2CFG);
+
+ /* Select DMA endianness (Host-endian: big-endian) */
+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
+ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
+ }
+
+ if (of_machine_is_compatible("lantiq,ar9")) {
+ /* Hard reset USB state machines */
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET)
+ | USBRESET_BIT | BIT(28), RCU_USBRESET);
+ udelay(50 * 1000);
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET)
+ & ~(USBRESET_BIT | BIT(28)), RCU_USBRESET);
+ } else {
+ /* Hard reset USB state machines */
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
+ udelay(50 * 1000);
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
+ }
- /* Configure cores to host mode */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
- RCU_USB1CFG);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
- RCU_USB2CFG);
-
- /* Select DMA endianness (Host-endian: big-endian) */
- ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
- | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
- ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
- | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
-
- /* Hard reset USB state machines */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
- udelay(50 * 1000);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
-
- /* Soft reset USB state machines */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
- | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
- udelay(50 * 1000);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
- & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
+ if (of_machine_is_compatible("lantiq,vr9")) {
+ /* Soft reset USB state machines */
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
+ | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
+ udelay(50 * 1000);
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
+ & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
+ }
}
static int __init mips_reboot_setup(void)
@@ -363,8 +420,11 @@ static int __init mips_reboot_setup(void
if (!ltq_rcu_membase)
panic("Failed to remap core memory");
- if (of_machine_is_compatible("lantiq,ar9") ||
- of_machine_is_compatible("lantiq,vr9"))
+ if (of_machine_is_compatible("lantiq,danube") ||
+ of_machine_is_compatible("lantiq,ase") ||
+ of_machine_is_compatible("lantiq,ar9") ||
+ of_machine_is_compatible("lantiq,vr9") ||
+ of_machine_is_compatible("lantiq,ar10"))
ltq_usb_init();
if (of_machine_is_compatible("lantiq,vr9"))
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -254,6 +254,25 @@ static void pmu_disable(struct clk *clk)
pr_warn("deactivating PMU module failed!");
}
+static void usb_set_clock(void)
+{
+ unsigned int val = ltq_cgu_r32(ifccr);
+
+ if (of_machine_is_compatible("lantiq,ar10") ||
+ of_machine_is_compatible("lantiq,grx390")) {
+ val &= ~0x03; /* XTAL divided by 3 */
+ } else if (of_machine_is_compatible("lantiq,ar9") ||
+ of_machine_is_compatible("lantiq,vr9")) {
+ /* TODO: this depends on the XTAL frequency */
+ val |= 0x03; /* XTAL divided by 3 */
+ } else if (of_machine_is_compatible("lantiq,ase")) {
+ val |= 0x20; /* from XTAL */
+ } else if (of_machine_is_compatible("lantiq,danube")) {
+ val |= 0x30; /* 12 MHz, generated from 36 MHz */
+ }
+ ltq_cgu_w32(val, ifccr);
+}
+
/* the pci enable helper */
static int pci_enable(struct clk *clk)
{
@@ -608,4 +627,5 @@ void __init ltq_soc_init(void)
if (of_machine_is_compatible("lantiq,vr9"))
xbar_fpi_burst_disable();
+ usb_set_clock();
}

View File

@ -1,93 +0,0 @@
--- a/drivers/mtd/ofpart.c
+++ b/drivers/mtd/ofpart.c
@@ -25,6 +25,38 @@ static bool node_has_compatible(struct d
return of_get_property(pp, "compatible", NULL);
}
+static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master,
+ loff_t offset)
+{
+ static uint8_t root_id;
+ int err, len;
+
+ err = mtd_read(master, offset, 0x01, &len, &root_id);
+
+ if (mtd_is_bitflip(err) || !err)
+ return &root_id;
+
+ return NULL;
+}
+
+static void brnboot_set_active_root_part(struct mtd_partition *pparts,
+ struct device_node **part_nodes,
+ int nr_parts,
+ uint8_t *root_id)
+{
+ int i;
+
+ for (i = 0; i < nr_parts; i++) {
+ int part_root_id;
+
+ if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id)
+ && part_root_id == *root_id) {
+ pparts[i].name = "firmware";
+ break;
+ }
+ }
+}
+
static int parse_ofpart_partitions(struct mtd_info *master,
struct mtd_partition **pparts,
struct mtd_part_parser_data *data)
@@ -35,7 +67,8 @@ static int parse_ofpart_partitions(struc
struct device_node *pp;
int nr_parts, i, ret = 0;
bool dedicated = true;
-
+ uint8_t *proot_id = NULL;
+ struct device_node **part_nodes;
if (!data)
return 0;
@@ -73,7 +106,9 @@ static int parse_ofpart_partitions(struc
return 0;
*pparts = kzalloc(nr_parts * sizeof(**pparts), GFP_KERNEL);
- if (!*pparts)
+ part_nodes = kzalloc(nr_parts * sizeof(*part_nodes), GFP_KERNEL);
+
+ if (!*pparts || !part_nodes)
return -ENOMEM;
i = 0;
@@ -121,12 +156,22 @@ static int parse_ofpart_partitions(struc
if (of_get_property(pp, "lock", &len))
(*pparts)[i].mask_flags |= MTD_POWERUP_LOCK;
+ if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector"))
+ proot_id = brnboot_get_selected_root_part(master, (*pparts)[i].offset);
+
+ part_nodes[i] = pp;
+
i++;
}
if (!nr_parts)
goto ofpart_none;
+ if (proot_id)
+ brnboot_set_active_root_part(*pparts, part_nodes, nr_parts, proot_id);
+
+ kfree(part_nodes);
+
return nr_parts;
ofpart_fail:
@@ -136,6 +181,7 @@ ofpart_fail:
ofpart_none:
of_node_put(pp);
kfree(*pparts);
+ kfree(part_nodes);
*pparts = NULL;
return ret;
}

View File

@ -1,48 +0,0 @@
From a32285ed4ba970b868b7fb49b716d776f4410ef6 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Sat, 19 Mar 2016 16:52:46 +0100
Subject: [PATCH] MIPS: lantiq: add support for device tree file from boot
loader
This fetches the device tree file like it is specified in the MIPS UHI
interface if one was found. This is also used when the device tree file
was appended to the kernel image with cat.
This code is copied from arch/mips/bmips/setup.c.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/mips/lantiq/prom.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -65,6 +65,8 @@ static void __init prom_init_cmdline(voi
void __init plat_mem_setup(void)
{
+ void *dtb;
+
ioport_resource.start = IOPORT_RESOURCE_START;
ioport_resource.end = IOPORT_RESOURCE_END;
iomem_resource.start = IOMEM_RESOURCE_START;
@@ -72,11 +74,18 @@ void __init plat_mem_setup(void)
set_io_port_base((unsigned long) KSEG1);
+ if (fw_arg0 == -2) /* UHI interface */
+ dtb = (void *)fw_arg1;
+ else if (__dtb_start != __dtb_end)
+ dtb = (void *)__dtb_start;
+ else
+ panic("no dtb found");
+
/*
- * Load the builtin devicetree. This causes the chosen node to be
+ * Load the devicetree. This causes the chosen node to be
* parsed resulting in our memory appearing
*/
- __dt_setup_arch(__dtb_start);
+ __dt_setup_arch(dtb);
}
void __init device_tree_init(void)

View File

@ -1,37 +0,0 @@
From 8cfe01de7d5c974165c1383fcc9e1dad6953341d Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Sat, 19 Mar 2016 17:06:00 +0100
Subject: [PATCH 2/2] MIPS: lantiq: make it possible to build in no device tree
Now it is possible to build in no device tree at all and depend on the
boot loader providing one or someone concatenating a device tree to the
end of the image.
This was copied from arch/mips/bmips/Kconfig
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/mips/lantiq/Kconfig | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -26,7 +26,17 @@ config SOC_FALCON
endchoice
choice
- prompt "Devicetree"
+ prompt "Built-in device tree"
+ help
+ Legacy bootloaders do not pass a DTB pointer to the kernel, so
+ if a "wrapper" is not being used, the kernel will need to include
+ a device tree that matches the target board.
+
+ The builtin DTB will only be used if the firmware does not supply
+ a valid DTB.
+
+config LANTIQ_DT_NONE
+ bool "None"
config DT_EASY50712
bool "Easy50712"

View File

@ -1,166 +0,0 @@
--- a/arch/mips/pci/ifxmips_pcie.c
+++ b/arch/mips/pci/ifxmips_pcie.c
@@ -18,6 +18,9 @@
#include <linux/pci_regs.h>
#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+
#include "ifxmips_pcie.h"
#include "ifxmips_pcie_reg.h"
@@ -40,6 +43,7 @@
static DEFINE_SPINLOCK(ifx_pcie_lock);
u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
+static int pcie_reset_gpio;
static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
{
@@ -82,6 +86,22 @@ void ifx_pcie_debug(const char *fmt, ...
printk("%s", buf);
}
+static inline void pcie_ep_gpio_rst_init(int pcie_port)
+{
+ gpio_direction_output(pcie_reset_gpio, 1);
+ gpio_set_value(pcie_reset_gpio, 1);
+}
+
+static inline void pcie_device_rst_assert(int pcie_port)
+{
+ gpio_set_value(pcie_reset_gpio, 0);
+}
+
+static inline void pcie_device_rst_deassert(int pcie_port)
+{
+ mdelay(100);
+ gpio_direction_output(pcie_reset_gpio, 1);
+}
static inline int pcie_ltssm_enable(int pcie_port)
{
@@ -1045,8 +1065,9 @@ pcie_rc_initialize(int pcie_port)
return 0;
}
-static int __init ifx_pcie_bios_init(void)
+static int ifx_pcie_bios_probe(struct platform_device *pdev)
{
+ struct device_node *node = pdev->dev.of_node;
void __iomem *io_map_base;
int pcie_port;
int startup_port;
@@ -1055,7 +1076,17 @@ static int __init ifx_pcie_bios_init(voi
pcie_ahb_pmu_setup();
startup_port = IFX_PCIE_PORT0;
-
+
+ pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
+ if (gpio_is_valid(pcie_reset_gpio)) {
+ int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset");
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio);
+ return ret;
+ }
+ gpio_direction_output(pcie_reset_gpio, 1);
+ }
+
for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
if (pcie_rc_initialize(pcie_port) == 0) {
IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n",
@@ -1067,6 +1098,7 @@ static int __init ifx_pcie_bios_init(voi
return -ENOMEM;
}
ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
+ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node);
register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
/* XXX, clear error status */
@@ -1083,6 +1115,30 @@ static int __init ifx_pcie_bios_init(voi
return 0;
}
+
+static const struct of_device_id ifxmips_pcie_match[] = {
+ { .compatible = "lantiq,pcie-xrx200" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ifxmips_pcie_match);
+
+static struct platform_driver ltq_pci_driver = {
+ .probe = ifx_pcie_bios_probe,
+ .driver = {
+ .name = "pcie-xrx200",
+ .owner = THIS_MODULE,
+ .of_match_table = ifxmips_pcie_match,
+ },
+};
+
+int __init ifx_pcie_bios_init(void)
+{
+ int ret = platform_driver_register(&ltq_pci_driver);
+ if (ret)
+ pr_info("pcie-xrx200: Error registering platform driver!");
+ return ret;
+}
+
arch_initcall(ifx_pcie_bios_init);
MODULE_LICENSE("GPL");
--- a/arch/mips/pci/ifxmips_pcie_vr9.h
+++ b/arch/mips/pci/ifxmips_pcie_vr9.h
@@ -22,8 +22,6 @@
#include <linux/gpio.h>
#include <lantiq_soc.h>
-#define IFX_PCIE_GPIO_RESET 494
-
#define IFX_REG_R32 ltq_r32
#define IFX_REG_W32 ltq_w32
#define CONFIG_IFX_PCIE_HW_SWAP
@@ -53,21 +51,6 @@
#define OUT ((volatile u32*)(IFX_GPIO + 0x0070))
-static inline void pcie_ep_gpio_rst_init(int pcie_port)
-{
-
- gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset");
- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
- gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
-
-/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
- ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
- ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
- ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
- ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
- ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/
-}
-
static inline void pcie_ahb_pmu_setup(void)
{
/* Enable AHB bus master/slave */
@@ -180,20 +163,6 @@ static inline void pcie_phy_rst_deassert
IFX_REG_W32(reg, IFX_RCU_RST_REQ);
}
-static inline void pcie_device_rst_assert(int pcie_port)
-{
- gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
-// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
-}
-
-static inline void pcie_device_rst_deassert(int pcie_port)
-{
- mdelay(100);
- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
-// gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
- //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
-}
-
static inline void pcie_core_pmu_setup(int pcie_port)
{
struct clk *clk;

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