添加aio-3399b的支持

2023-09-13 06:48:38 +00:00 · 2023-09-13 06:48:38 +00:00 · 0d83e7e546
parent e2b6e2a3dd
commit 0d83e7e546
36 changed files with 3384 additions and 614 deletions
--- a/package/boot/arm-trusted-firmware-rockchip-vendor/Makefile
+++ b/package/boot/arm-trusted-firmware-rockchip-vendor/Makefile
@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2022 ImmortalWrt.org
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=arm-trusted-firmware-rockchip-vendor
+PKG_RELEASE:=$(AUTORELEASE)
+
+PKG_SOURCE_PROTO:=git
+
+ifeq ($(HOST_ARCH),aarch64)
+PKG_SOURCE_VERSION:=9f843531d8dae25772efff7590908e974cf48540
+PKG_MIRROR_HASH:=7699938adb7d5fe4f73aacd8082b497dca3eb288d6198edeb86209d14b5d83d7
+PKG_SOURCE_URL=http://gits.kos.org.cn:3000/k/rkbin.git
+PKG_SOURCE_DATE:=2023-05-31
+else
+PKG_SOURCE_URL=https://github.com/rockchip-linux/rkbin.git
+PKG_SOURCE_DATE:=2023-07-26
+PKG_SOURCE_VERSION:=b4558da0860ca48bf1a571dd33ccba580b9abe23
+PKG_MIRROR_HASH:=50e904a9d53466449155ff8f80522ffdfe7fb36a2ff13055416259e1468c07bf
+endif
+
+PKG_MAINTAINER:=Tianling Shen <cnsztl@immortalwrt.org>
+
+MAKE_PATH:=$(PKG_NAME)
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/arm-trusted-firmware-rockchip-vendor
+    SECTION:=boot
+    CATEGORY:=Boot Loaders
+    TITLE:=ARM Trusted Firmware for Rockchip
+endef
+
+define Package/arm-trusted-firmware-rk3328
+    $(Package/arm-trusted-firmware-rockchip-vendor)
+    DEPENDS:=@TARGET_rockchip_armv8
+    VARIANT:=rk3328
+endef
+
+define Package/arm-trusted-firmware-rk3399
+    $(Package/arm-trusted-firmware-rockchip-vendor)
+    DEPENDS:=@TARGET_rockchip_armv8
+    VARIANT:=rk3399
+endef
+
+define Package/arm-trusted-firmware-rk3566
+    $(Package/arm-trusted-firmware-rockchip-vendor)
+    DEPENDS:=@TARGET_rockchip_armv8
+    VARIANT:=rk3566
+endef
+
+define Package/arm-trusted-firmware-rk3568
+    $(Package/arm-trusted-firmware-rockchip-vendor)
+    DEPENDS:=@TARGET_rockchip_armv8
+    VARIANT:=rk3568
+endef
+
+define Build/Configure
+	$(SED) 's,$$$$(PKG_BUILD_DIR),$(PKG_BUILD_DIR),g' $(PKG_BUILD_DIR)/trust.ini
+	$(SED) 's,$$$$(VARIANT),$(BUILD_VARIANT),g' $(PKG_BUILD_DIR)/trust.ini
+	$(call Build/Configure/Default)
+endef
+
+define Build/Compile
+	$(CURDIR)/pack-firmware.sh build $(BUILD_VARIANT) '$(PKG_BUILD_DIR)'
+endef
+
+define Build/InstallDev
+	$(CURDIR)/pack-firmware.sh install $(BUILD_VARIANT) '$(PKG_BUILD_DIR)' '$(STAGING_DIR_IMAGE)'
+endef
+
+define Package/arm-trusted-firmware-rk3328/install
+endef
+
+define Package/arm-trusted-firmware-rk3399/install
+endef
+
+define Package/arm-trusted-firmware-rk3566/install
+endef
+
+define Package/arm-trusted-firmware-rk3568/install
+endef
+
+$(eval $(call BuildPackage,arm-trusted-firmware-rk3328))
+$(eval $(call BuildPackage,arm-trusted-firmware-rk3399))
+$(eval $(call BuildPackage,arm-trusted-firmware-rk3566))
+$(eval $(call BuildPackage,arm-trusted-firmware-rk3568))
--- a/package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh
+++ b/package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh
@ -0,0 +1,64 @@
+#!/bin/bash
+# Copyright (C) 2021 ImmortalWrt.org
+
+ACTION="$1"
+VARIANT="$2"
+PKG_BUILD_DIR="$3"
+STAGING_DIR_IMAGE="$4"
+
+case "$VARIANT" in
+"rk3328")
+	ATF="rk33/rk322xh_bl31_v1.49.elf"
+	DDR="rk33/rk3328_ddr_333MHz_v1.19.bin"
+	LOADER="rk33/rk322xh_miniloader_v2.50.bin"
+	;;
+"rk3399")
+	ATF="rk33/rk3399_bl31_v1.36.elf"
+	DDR="rk33/rk3399_ddr_800MHz_v1.30.bin"
+	LOADER="rk33/rk3399_miniloader_v1.30.bin"
+	;;
+"rk3566")
+	ATF="rk35/rk3568_bl31_v1.43.elf"
+	DDR="rk35/rk3566_ddr_1056MHz_v1.18.bin"
+	;;
+"rk3568")
+	ATF="rk35/rk3568_bl31_v1.43.elf"
+	DDR="rk35/rk3568_ddr_1560MHz_v1.18.bin"
+	;;
+"rk3588")
+	ATF="rk35/rk3588_bl31_v1.40.elf"
+	DDR="rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.12.bin"
+	;;
+*)
+	echo -e "Not compatible with your platform: $VARIANT."
+	exit 1
+	;;
+esac
+
+set -x
+if [ "$ACTION" == "build" ]; then
+	case "$VARIANT" in
+	rk33*)
+		"$PKG_BUILD_DIR"/tools/mkimage -n "$VARIANT" -T "rksd" -d "$PKG_BUILD_DIR/bin/$DDR" "$PKG_BUILD_DIR/$VARIANT-idbloader.bin"
+		cat "$PKG_BUILD_DIR/bin/$LOADER" >> "$PKG_BUILD_DIR/$VARIANT-idbloader.bin"
+		"$PKG_BUILD_DIR/tools/trust_merger" --replace "bl31.elf" "$PKG_BUILD_DIR/bin/$ATF" "$PKG_BUILD_DIR/trust.ini"
+		;;
+	esac
+elif [ "$ACTION" == "install" ]; then
+	mkdir -p "$STAGING_DIR_IMAGE"
+	cp -fp "$PKG_BUILD_DIR/bin/$ATF" "$STAGING_DIR_IMAGE"/
+	case "$VARIANT" in
+	rk33*)
+		cp -fp "$PKG_BUILD_DIR/tools/loaderimage" "$STAGING_DIR_IMAGE"/
+		cp -fp "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" "$STAGING_DIR_IMAGE"/
+		cp -fp "$PKG_BUILD_DIR/$VARIANT-trust.bin" "$STAGING_DIR_IMAGE"/
+		;;
+	rk35*)
+		cp -fp "$PKG_BUILD_DIR/bin/$DDR" "$STAGING_DIR_IMAGE"/
+		;;
+	esac
+else
+	echo -e "Unknown operation: $ACTION."
+	exit 1
+fi
+set +x
--- a/package/boot/arm-trusted-firmware-rockchip-vendor/src/trust.ini
+++ b/package/boot/arm-trusted-firmware-rockchip-vendor/src/trust.ini
@ -0,0 +1,15 @@
+[VERSION]
+MAJOR=1
+MINOR=0
+[BL30_OPTION]
+SEC=0
+[BL31_OPTION]
+SEC=1
+PATH=bl31.elf
+ADDR=0x10000
+[BL32_OPTION]
+SEC=0
+[BL33_OPTION]
+SEC=0
+[OUTPUT]
+PATH=$(PKG_BUILD_DIR)/$(VARIANT)-trust.bin
--- a/package/boot/uboot-rockchip/Makefile
+++ b/package/boot/uboot-rockchip/Makefile
@ -74,6 +74,16 @@ define U-Boot/rk3399/Default
  ATF:=rk3399_bl31.elf
 endef

+define U-Boot/aio-3399b-rk3399
+  BUILD_SUBTARGET:=armv8
+  DEPENDS:=+PACKAGE_u-boot-$(1):arm-trusted-firmware-rk3399
+  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+  ATF:=rk3399_bl31_v1.36.elf
+  USE_RKBIN:=1
+  NAME:=AIO-3399B
+  BUILD_DEVICES:= \
+    aio-3399b
+endef
 define U-Boot/nanopi-r4s-rk3399
  $(U-Boot/rk3399/Default)
  NAME:=NanoPi R4S
@ -96,6 +106,7 @@ define U-Boot/rockpro64-rk3399
 endef

 UBOOT_TARGETS := \
+  aio-3399b-rk3399\
  nanopi-r4s-rk3399 \
  rock-pi-4-rk3399 \
  rockpro64-rk3399 \
@ -108,6 +119,7 @@ UBOOT_TARGETS := \
 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes

 UBOOT_MAKE_FLAGS += \
+  PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \
  BL31=$(STAGING_DIR_IMAGE)/$(ATF)

 define Build/Configure
@ -121,14 +133,21 @@ ifneq ($(OF_PLATDATA),)
 	$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h
 	$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-decl.h $(PKG_BUILD_DIR)/include/generated/dt-decl.h
 endif
-
+ifeq ($(USE_RKBIN),1)
+	$(SED) 's#CONFIG_IDENT_STRING=.*#CONFIG_IDENT_STRING="OpenWrt"#g' $(PKG_BUILD_DIR)/.config
+endif
 	$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config
 endef

 define Build/InstallDev
 	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
+ifeq ($(USE_RKBIN),1)
+	$(STAGING_DIR_IMAGE)/loaderimage --pack --uboot $(PKG_BUILD_DIR)/u-boot-dtb.bin $(PKG_BUILD_DIR)/uboot.img 0x200000
+	$(CP) $(PKG_BUILD_DIR)/uboot.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-uboot.img
+else
 	$(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img
 	$(CP) $(PKG_BUILD_DIR)/u-boot.itb $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.itb
+endif
 endef

 define Package/u-boot/install/default
--- a/package/boot/uboot-rockchip/patches/308-rockchip-rk3399-Add-support-for-aio-3399b.patch
+++ b/package/boot/uboot-rockchip/patches/308-rockchip-rk3399-Add-support-for-aio-3399b.patch
@ -0,0 +1,10 @@
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -146,5 +146,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
+ 	rk3399-rock-pi-4b.dtb \
+ 	rk3399-rock-pi-4c.dtb \
+ 	rk3399-rock960.dtb \
+	rk3399-aio-3399b.dtb \
+ 	rk3399-rockpro64.dtb \
+ 	rk3399pro-rock-pi-n10.dtb
+
--- a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-aio-3399b-u-boot.dtsi
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-aio-3399b-u-boot.dtsi
@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-ddr3-1600.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+/ {
+	chosen {
+		u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+	};
+};
+
+&vdd_log {
+	regulator-init-microvolt = <950000>;
+};
--- a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-aio-3399b.dts
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3399-aio-3399b.dts
--- a/package/boot/uboot-rockchip/src/configs/aio-3399b-rk3399_defconfig
+++ b/package/boot/uboot-rockchip/src/configs/aio-3399b-rk3399_defconfig
@ -0,0 +1,76 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-aio-3399b"
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-aio-3399b.dtb"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SENSORS_PWM_FAN=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_SENSORS_PWM_FAN=y
+CONFIG_MISC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
--- a/package/firmware/linux-firmware/brcm_firmware/ap6236/brcmfmac43430-sdio.bin
+++ b/package/firmware/linux-firmware/brcm_firmware/ap6236/brcmfmac43430-sdio.bin
--- a/package/firmware/linux-firmware/brcm_firmware/ap6236/brcmfmac43430-sdio.txt
+++ b/package/firmware/linux-firmware/brcm_firmware/ap6236/brcmfmac43430-sdio.txt
@ -0,0 +1,54 @@
+#AP6212_NVRAM_V1.0_20140603
+# 2.4 GHz, 20 MHz BW mode
+
+# The following parameter values are just placeholders, need to be updated.
+manfid=0x2d0
+prodid=0x0726
+vendid=0x14e4
+devid=0x43e2
+boardtype=0x0726
+boardrev=0x1101
+boardnum=22
+macaddr=00:90:4c:c5:12:38
+sromrev=11
+boardflags=0x00404201
+xtalfreq=26000
+nocrc=1
+ag0=255
+aa2g=1
+ccode=ALL
+
+pa0itssit=0x20
+extpagain2g=0
+
+#PA parameters for 2.4GHz, measured at CHIP OUTPUT
+pa2ga0=-168,7161,-820
+AvVmid_c0=0x0,0xc8
+cckpwroffset0=5
+
+# PPR params
+maxp2ga0=90
+txpwrbckof=6
+cckbw202gpo=0x5555
+legofdmbw202gpo=0x77777777
+mcsbw202gpo=0xaaaaaaaa
+
+# OFDM IIR :
+ofdmdigfilttype=7
+# PAPD mode:
+papdmode=2
+
+il0macaddr=00:90:4c:c5:12:38
+wl0id=0x431b
+
+#OOB parameters
+hostwake=0x40
+hostrdy=0x41
+usbrdy=0x03
+usbrdydelay=100
+deadman_to=0xffffffff
+# muxenab: 0x1 for UART enable, 0x10 for Host awake
+muxenab=0x10
+# CLDO PWM voltage settings - 0x4 - 1.1 volt
+#cldo_pwm=0x4
+
--- a/package/firmware/linux-firmware/brcm_firmware/ap6275s/BCM4362A2.hcd
+++ b/package/firmware/linux-firmware/brcm_firmware/ap6275s/BCM4362A2.hcd
--- a/package/firmware/linux-firmware/brcm_firmware/ap6275s/clm_bcm43752a2_ag.blob
+++ b/package/firmware/linux-firmware/brcm_firmware/ap6275s/clm_bcm43752a2_ag.blob
--- a/package/firmware/linux-firmware/brcm_firmware/ap6275s/fw_bcm43752a2_ag_apsta.bin
+++ b/package/firmware/linux-firmware/brcm_firmware/ap6275s/fw_bcm43752a2_ag_apsta.bin
--- a/package/firmware/linux-firmware/brcm_firmware/ap6275s/nvram_ap6275s.txt
+++ b/package/firmware/linux-firmware/brcm_firmware/ap6275s/nvram_ap6275s.txt
@ -0,0 +1,354 @@
+# AP6275S_NVRAM_V1.8_20210824
+# AP6275S v00 WLBGA reference board, iPA version.
+
+# SSID generated using Alberto's boardssid.py script:
+# ********************SUMMARY********************
+# Board Name: AP6275S_V00
+#SSID: 0x086d
+#macmid: 0x02df
+# Successfully made SSID entry in sromdefs.tcl.
+# Successfully made macmid entry in sromdefs.tcl.
+# Successfully made SSID entry in tblssid.py.
+# *************************************************
+# $ Copyright Broadcom $
+#
+#
+# <<Broadcom-WL-IPTag/Proprietary:>>
+NVRAMRev=$Rev: 844050 $
+sromrev=11
+boardrev=0x1213
+boardtype=0x08ed
+boardflags=0x00400201
+boardflags2=0xc0800000
+boardflags3=0x40002180
+#boardnum=57410
+macaddr=00:90:4c:12:d0:01
+jtag_irw=38
+
+#Regulatory specific
+ccode=0
+regrev=0
+
+# Board specific
+vendid=0x14e4
+devid=0x449d
+manfid=0x2d0
+antswitch=0
+pdgain5g=0
+pdgain2g=0
+aa2g=3
+aa5g=3
+agbg0=2
+agbg1=2
+aga0=2
+aga1=2
+extpagain2g=2
+extpagain5g=2
+rxgains2gelnagaina0=0
+rxgains2gtrisoa0=0
+rxgains2gtrelnabypa0=0
+rxgains5gelnagaina0=0
+rxgains5gtrisoa0=0
+rxgains5gtrelnabypa0=0
+rxgains5gmelnagaina0=0
+rxgains5gmtrisoa0=0
+rxgains5gmtrelnabypa0=0
+rxgains5ghelnagaina0=0
+rxgains5ghtrisoa0=0
+rxgains5ghtrelnabypa0=0
+rxgains2gelnagaina1=0
+rxgains2gtrisoa1=0
+rxgains2gtrelnabypa1=0
+rxgains5gelnagaina1=0
+rxgains5gtrisoa1=0
+rxgains5gtrelnabypa1=0
+rxgains5gmelnagaina1=0
+rxgains5gmtrisoa1=0
+rxgains5gmtrelnabypa1=0
+rxgains5ghelnagaina1=0
+rxgains5ghtrisoa1=0
+rxgains5ghtrelnabypa1=0
+
+#RSSI related
+# 2G
+rssicorrnorm_c0=4,4
+rssicorrnorm_c1=4,4
+# 5G
+rssicorrnorm5g_c0=5,5,5,5,5,5,5,5,5,5,5,5
+rssicorrnorm5g_c1=4,4,4,4,4,4,4,4,4,4,4,4
+
+
+#Two range TSSI
+tworangetssi2g=0
+tworangetssi5g=0
+lowpowerrange2g=0
+lowpowerrange5g=0
+low_adc_rate_en=1
+# NOTE :================================================================================
+# To run TPC with Two Range TSSI ,set  tworangetssi2g = 1 and lowpowerrange2g = 0
+# To run TPC with Single Range TSSI, set tworangetssi2g = 0
+# To run TPC please READ instructions near pa2ga0 and pa2ga1 as well
+# To generate PA params for Low Range set  tworangetssi2g = 0 and lowpowerrange2g to 1
+# To generate PA params for High Range set  tworangetssi2g = 1 and lowpowerrange2g to 1
+# ======================================================================================
+
+#Related to FW Download. Host may use this
+nocrc=1
+
+otpimagesize=502
+
+xtalfreq=37400
+
+txchain=3
+rxchain=3
+
+cckdigfilttype=2
+
+#bit mask for slice capability bit 0:2G bit 1:5G
+bandcap=3
+
+#TXBF Related
+rpcal2g=0
+rpcal5gb0=0
+rpcal5gb1=0
+rpcal5gb2=0
+rpcal5gb3=0
+
+
+#FDSS Related
+fdss_level_2g=4,4
+fdss_interp_en=1
+fdss_level_5g=4,4
+fdss_level_11ax_2g=3,3
+fdss_level_11ax_2g_ch1=3,3
+fdss_level_11ax_2g_ch11=3,3
+fdss_level_11ax_5g=3,3
+
+#Tempsense Related
+tempthresh=255
+tempoffset=40
+rawtempsense=0x1ff
+phycal_tempdelta=15
+temps_period=15
+temps_hysteresis=15
+
+#------------- TSSI Related -------------
+
+tssipos2g=1
+tssipos5g=1
+AvVmid_c0=2,127,4,92,4,91,4,91,4,94
+AvVmid_c1=2,127,4,93,4,93,4,95,3,110
+# CCK in case of multi mode 2
+pa2gccka0=-107,8241,-929
+pa2gccka1=-86,8682,-961
+# OFDM in case of multi_mode 2
+pa2ga0=-92,7647,-831
+pa2ga1=-115,7023,-766
+pa5ga0=-175,5735,-699,-194,5574,-689,-160,6066,-727,-176,5834,-714
+pa5ga1=-163,5928,-712,-193,5622,-695,-188,5523,-688,-170,6097,-749
+
+# Max power and offsets
+maxp2ga0=94
+maxp2ga1=86
+maxp5ga0=69,68,68,69
+maxp5ga1=69,68,68,69
+subband5gver=0x4
+paparambwver=3
+cckpwroffset0=0
+cckpwroffset1=0
+pdoffset40ma0=0x0000
+pdoffset80ma0=0x0100
+pdoffset40ma1=0x1111
+pdoffset80ma1=0x1010
+cckbw202gpo=0x1111
+cckbw20ul2gpo=0x0000
+mcsbw202gpo=0x77544331
+mcsbw402gpo=0x00000000
+dot11agofdmhrbw202gpo=0x4433
+ofdmlrbw202gpo=0x1111
+mcsbw205glpo=0x66200000
+mcsbw405glpo=0x94100000
+mcsbw805glpo=0x99221111
+mcsbw1605glpo=0
+mcsbw205gmpo=0x66200000
+mcsbw405gmpo=0x94100000
+mcsbw805gmpo=0x99221111
+mcsbw1605gmpo=0
+mcsbw205ghpo=0x66200000
+mcsbw405ghpo=0xA5211111
+mcsbw805ghpo=0xBB221111
+powoffs2gtna0=0,0,0,0,0,0,0,0,0,0,0,0,0,0
+powoffs2gtna1=-1,-1,-1,0,0,0,0,0,0,0,0,0,0,0
+mcs1024qam2gpo=0xCCAA
+mcs1024qam5glpo=0xDDDDAA
+mcs1024qam5gmpo=0xDDDDAA
+mcs1024qam5ghpo=0xDDFFCC
+mcs1024qam5gx1po=0xEECCCC
+mcs1024qam5gx2po=0xEECCCC
+mcs8poexp=0
+mcs9poexp=0
+mcs10poexp=0
+
+# 5G power offset per channel for band edge channel
+powoffs5g20mtna0=0,0,0,0,0,0,0
+powoffs5g20mtna1=0,0,0,0,0,0,0
+powoffs5g40mtna0=0,0,0,0,0
+powoffs5g40mtna1=0,0,0,0,0
+powoffs5g80mtna0=0,0,0,0,0
+powoffs5g80mtna1=0,0,0,0,0
+mcs11poexp=0
+
+#LTE Coex Related
+ltecxmux=0
+ltecxpadnum=0x0504
+ltecxfnsel=0x44
+ltecxgcigpio=0x04
+#OOB params
+#device_wake_opt=1
+host_wake_opt=0
+
+# SWCTRL Related
+
+swctrlmap_2g=0x10101010,0x06030401,0x04011010,0x000000,0x3FF
+swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000
+swctrlmap_5g=0x80408040,0x21240120,0x01208040,0x000000,0x3FF
+swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000
+clb2gslice0core0=0x01b
+clb2gslice1core0=0x000
+clb5gslice0core0=0x064
+clb5gslice1core0=0x000
+clb2gslice0core1=0x056
+clb2gslice1core1=0x000
+clb5gslice0core1=0x0a1
+clb5gslice1core1=0x000
+btc_prisel_ant_mask=0x2
+clb_swctrl_smask_ant0=0x27f
+clb_swctrl_smask_ant1=0x2f7
+
+
+#BT Coex 1:TDM
+btc_mode=1
+
+# --- PAPD Cal related params ----
+txwbpapden=0 # 0:NBPAPD 1:WBPAPD
+# NB PAPD Cal params
+nb_eps_offset=470,470
+nb_bbmult=66,66
+nb_papdcalidx=6,6
+nb_txattn=2,2
+nb_rxattn=1,1
+nb_eps_stopidx=63
+epsilonoff_5g20_c0=2,2,2,0
+epsilonoff_5g40_c0=2,2,2,0
+epsilonoff_5g80_c0=2,2,2,0
+epsilonoff_5g20_c1=0,0,-2,-2
+epsilonoff_5g40_c1=0,0,0,-2
+epsilonoff_5g80_c1=0,0,-2,-2
+epsilonoff_2g20_c0=0
+epsilonoff_2g20_c1=0
+
+# energy detect threshold
+ed_thresh2g=-67
+ed_thresh5g=-67
+# energy detect threshold for EU
+eu_edthresh2g=-67
+eu_edthresh5g=-67
+
+#rpcal coef for imptxbf
+rpcal5gb0=238
+rpcal5gb1=228
+rpcal5gb2=222
+rpcal5gb3=229
+rpcal2g=15
+ocl=0
+bt_coex_chdep_div=1
+
+# OLPC Related
+disable_olpc=0
+olpc_thresh5g=32
+olpc_anchor5g=40
+olpc_thresh2g=32
+olpc_anchor2g=40
+
+#PAPR related
+paprdis=0
+paprrmcsgamma2g=500,550,550,-1,-1,-1,-1,-1,-1,-1,-1,-1
+paprrmcsgain2g=128,128,128,0,0,0,0,0,0,0,0,0
+paprrmcsgamma2g_ch13=500,550,550,-1,-1,-1,-1,-1,-1,-1,-1,-1
+paprrmcsgain2g_ch13=128,128,128,0,0,0,0,0,0,0,0,0
+paprrmcsgamma2g_ch1=500,550,550,-1,-1,-1,-1,-1,-1,-1,-1,-1
+paprrmcsgain2g_ch1=128,128,128,0,0,0,0,0,0,0,0,0
+paprrmcsgamma5g20=500,500,500,-1,-1,-1,-1,-1,-1,-1,-1,-1
+paprrmcsgain5g20=128,128,128,0,0,0,0,0,0,0,0,0
+paprrmcsgamma5g40=600,600,600,-1,-1,-1,-1,-1,-1,-1,-1,-1
+paprrmcsgain5g40=128,128,128,0,0,0,0,0,0,0,0,0
+paprrmcsgamma5g80=-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1
+paprrmcsgain5g80=0,0,0,0,0,0,0,0,0,0,0,0
+
+# Enable papd for cck when target pwr ge 16dBm
+cckpapd_pwrthresh=64
+
+## ULOFDMA Board limit PPRs for 2G20 ##
+ruppr2g20bpska0=0x8421
+ruppr2g20bpska1=0x8421
+ruppr2g20qpska0=0x8421
+ruppr2g20qpska1=0x8421
+ruppr2g20qam16a0=0x10842
+ruppr2g20qam16a1=0x10842
+ruppr2g20qam64a0=0x18C63
+ruppr2g20qam64a1=0x18C63
+ruppr2g20qam256a0=0x21084
+ruppr2g20qam256a1=0x21084
+ruppr2g20qam1024a0=0x5294A
+ruppr2g20qam1024a1=0x5294A
+## ULOFDMA Board limit PPRs for 5G20 ##
+ruppr5g20bpska0=0x18000
+ruppr5g20bpska1=0x18000
+ruppr5g20qpska0=0x18000
+ruppr5g20qpska1=0x18000
+ruppr5g20qam16a0=0x18000
+ruppr5g20qam16a1=0x18000
+ruppr5g20qam64a0=0x18842
+ruppr5g20qam64a1=0x18842
+ruppr5g20qam256a0=0x318C6
+ruppr5g20qam256a1=0x318C6
+ruppr5g20qam1024a0=0x6318C
+ruppr5g20qam1024a1=0x6318C
+## ULOFDMA Board limit PPRs for 5G40 ##
+ruppr5g40bpska0=0x308421
+ruppr5g40bpska1=0x308421
+ruppr5g40qpska0=0x308421
+ruppr5g40qpska1=0x308421
+ruppr5g40qam16a0=0x308421
+ruppr5g40qam16a1=0x308421
+ruppr5g40qam64a0=0x308421
+ruppr5g40qam64a1=0x308421
+ruppr5g40qam256a0=0x739CE7
+ruppr5g40qam256a1=0x739CE7
+ruppr5g40qam1024a0=0xD6B5AD
+ruppr5g40qam1024a1=0xD6B5AD
+## ULOFDMA Board limit PPRs for 5G80 ##
+ruppr5g80bpska0=0x4108421
+ruppr5g80bpska1=0x4108421
+ruppr5g80qpska0=0x4108421
+ruppr5g80qpska1=0x4108421
+ruppr5g80qam16a0=0x4108421
+ruppr5g80qam16a1=0x4108421
+ruppr5g80qam64a0=0x8108421
+ruppr5g80qam64a1=0x8108421
+ruppr5g80qam256a0=0x1C7398C6
+ruppr5g80qam256a1=0x1C7398C6
+ruppr5g80qam1024a0=0x38C6318C
+ruppr5g80qam1024a1=0x38C6318C
+
+muxenab=0x10
+
+# ###########  BTC Dynctl profile params  ############
+# flags:bit0 - dynctl enabled, bit1 dynamic desense, bit2 dynamic mode, bit 3 TX power control
+#btcdyn_flags=1
+
+#btcdyn_default_btc_mode=5
+#btcdyn_msw_rows=0
+#btcdyn_dsns_rows=0
+#btc_params1007=100
+#btc_params1017=4
--- a/package/firmware/linux-firmware/brcm_firmware/ap6356s/brcmfmac4356-sdio.rongpin,king3399.bin
+++ b/package/firmware/linux-firmware/brcm_firmware/ap6356s/brcmfmac4356-sdio.rongpin,king3399.bin
--- a/package/firmware/linux-firmware/brcm_firmware/ap6356s/brcmfmac4356-sdio.rongpin,king3399.txt
+++ b/package/firmware/linux-firmware/brcm_firmware/ap6356s/brcmfmac4356-sdio.rongpin,king3399.txt
@ -0,0 +1,125 @@
+# Sample variables file for BCM94356Z NGFF 22x30mm iPA, iLNA board with PCIe for production package
+NVRAMRev=$Rev: 492104 $
+#4356 chip = 4354 A2 chip
+sromrev=11
+boardrev=0x1102
+boardtype=0x073e
+boardflags=0x02400201
+#0x2000 enable 2G spur WAR
+boardflags2=0x00802000
+boardflags3=0x0000000a
+#boardflags3 0x00000100 /* to read swctrlmap from nvram*/
+#define BFL3_5G_SPUR_WAR   0x00080000   /* enable spur WAR in 5G band */
+#define BFL3_AvVim   0x40000000   /* load AvVim from nvram */
+macaddr=00:90:4c:1a:10:01
+ccode=0x5854
+regrev=205
+antswitch=0
+pdgain5g=4
+pdgain2g=4
+tworangetssi2g=0
+tworangetssi5g=0
+paprdis=0
+femctrl=10
+vendid=0x14e4
+devid=0x43ec
+manfid=0x2d0
+#prodid=0x052e
+nocrc=1
+otpimagesize=502
+xtalfreq=37400
+rxgains2gelnagaina0=0
+rxgains2gtrisoa0=7
+rxgains2gtrelnabypa0=0
+rxgains5gelnagaina0=0
+rxgains5gtrisoa0=11
+rxgains5gtrelnabypa0=0
+rxgains5gmelnagaina0=0
+rxgains5gmtrisoa0=13
+rxgains5gmtrelnabypa0=0
+rxgains5ghelnagaina0=0
+rxgains5ghtrisoa0=12
+rxgains5ghtrelnabypa0=0
+rxgains2gelnagaina1=0
+rxgains2gtrisoa1=7
+rxgains2gtrelnabypa1=0
+rxgains5gelnagaina1=0
+rxgains5gtrisoa1=10
+rxgains5gtrelnabypa1=0
+rxgains5gmelnagaina1=0
+rxgains5gmtrisoa1=11
+rxgains5gmtrelnabypa1=0
+rxgains5ghelnagaina1=0
+rxgains5ghtrisoa1=11
+rxgains5ghtrelnabypa1=0
+rxchain=3
+txchain=3
+aa2g=3
+aa5g=3
+agbg0=2
+agbg1=2
+aga0=2
+aga1=2
+tssipos2g=1
+extpagain2g=2
+tssipos5g=1
+extpagain5g=2
+tempthresh=255
+tempoffset=255
+rawtempsense=0x1ff
+pa2ga0=-147,6192,-705
+pa2ga1=-161,6041,-701
+pa5ga0=-194,6069,-739,-188,6137,-743,-185,5931,-725,-171,5898,-715
+pa5ga1=-190,6248,-757,-190,6275,-759,-190,6225,-757,-184,6131,-746
+subband5gver=0x4
+pdoffsetcckma0=0x4
+pdoffsetcckma1=0x4
+pdoffset40ma0=0x0000
+pdoffset80ma0=0x0000
+pdoffset40ma1=0x0000
+pdoffset80ma1=0x0000
+maxp2ga0=76
+maxp5ga0=74,74,74,74
+maxp2ga1=76
+maxp5ga1=74,74,74,74
+cckbw202gpo=0x0000
+cckbw20ul2gpo=0x0000
+mcsbw202gpo=0x99644422
+mcsbw402gpo=0x99644422
+dot11agofdmhrbw202gpo=0x6666
+ofdmlrbw202gpo=0x0022
+mcsbw205glpo=0x88766663
+mcsbw405glpo=0x88666663
+mcsbw805glpo=0xbb666665
+mcsbw205gmpo=0xd8666663
+mcsbw405gmpo=0x88666663
+mcsbw805gmpo=0xcc666665
+mcsbw205ghpo=0xdc666663
+mcsbw405ghpo=0xaa666663
+mcsbw805ghpo=0xdd666665
+mcslr5glpo=0x0000
+mcslr5gmpo=0x0000
+mcslr5ghpo=0x0000
+sb20in40hrpo=0x0
+sb20in80and160hr5glpo=0x0
+sb40and80hr5glpo=0x0
+sb20in80and160hr5gmpo=0x0
+sb40and80hr5gmpo=0x0
+sb20in80and160hr5ghpo=0x0
+sb40and80hr5ghpo=0x0
+sb20in40lrpo=0x0
+sb20in80and160lr5glpo=0x0
+sb40and80lr5glpo=0x0
+sb20in80and160lr5gmpo=0x0
+sb40and80lr5gmpo=0x0
+sb20in80and160lr5ghpo=0x0
+sb40and80lr5ghpo=0x0
+dot11agduphrpo=0x0
+dot11agduplrpo=0x0
+phycal_tempdelta=255
+temps_period=15
+temps_hysteresis=15
+rssicorrnorm_c0=4,4
+rssicorrnorm_c1=4,4
+rssicorrnorm5g_c0=1,2,3,1,2,3,6,6,8,6,6,8
+rssicorrnorm5g_c1=1,2,3,2,2,2,7,7,8,7,7,8
--- a/package/firmware/linux-firmware/broadcom.mk
+++ b/package/firmware/linux-firmware/broadcom.mk
@ -188,3 +188,15 @@ define Package/bnx2x-firmware/install
 		$(1)/lib/firmware/bnx2x/
 endef
 $(eval $(call BuildPackage,bnx2x-firmware))
+
+Package/aio-3399b-firmware = $(call Package/firmware-default,Broadcom FullMac SDIO firmware)
+define Package/aio-3399b-firmware/install
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(INSTALL_DATA) ./brcm_firmware/ap6356s/brcmfmac4356-sdio.rongpin,king3399.bin $(1)/lib/firmware/brcm/brcmfmac4356-sdio.aio,aio-3399b.bin
+	$(INSTALL_DATA) ./brcm_firmware/ap6356s/brcmfmac4356-sdio.rongpin,king3399.txt $(1)/lib/firmware/brcm/brcmfmac4356-sdio.aio,aio-3399b.txt
+	$(INSTALL_DATA) ./brcm_firmware/ap6275s/BCM4362A2.hcd $(1)/lib/firmware/brcm/BCM4362A2.hcd
+	$(INSTALL_DATA) ./brcm_firmware/ap6275s/clm_bcm43752a2_ag.blob $(1)/lib/firmware/brcm/brcmfmac43752-sdio.clm_blob
+	$(INSTALL_DATA) ./brcm_firmware/ap6275s/fw_bcm43752a2_ag_apsta.bin $(1)/lib/firmware/brcm/brcmfmac43752-sdio.aio,aio-3399b.bin
+	$(INSTALL_DATA) ./brcm_firmware/ap6275s/nvram_ap6275s.txt $(1)/lib/firmware/brcm/brcmfmac43752-sdio.aio,aio-3399b.txt
+endef
+$(eval $(call BuildPackage,aio-3399b-firmware))
--- a/package/kernel/mac80211/broadcom.mk
+++ b/package/kernel/mac80211/broadcom.mk
@ -432,7 +432,7 @@ define KernelPackage/brcmfmac/config
 		default y if TARGET_bcm27xx
 		default y if TARGET_imx_cortexa7
 		default y if TARGET_sunxi
-		default n
+		default y
 		help
 		  Enable support for cards attached to an SDIO bus.
 		  Select this option only if you are sure that your
--- a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c
+++ b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c
@ -256,7 +256,7 @@ static int __rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)

 int __rtl8366_mdio_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
 {
-	u32 phy_id = MDC_REALTEK_PHY_ADDR;
+	u32 phy_id = smi->phy_id ? smi->phy_id : MDC_REALTEK_PHY_ADDR;
 	struct mii_bus *mbus = smi->ext_mbus;

 	BUG_ON(in_interrupt());
@ -293,7 +293,7 @@ int __rtl8366_mdio_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)

 static int __rtl8366_mdio_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
 {
-	u32 phy_id = MDC_REALTEK_PHY_ADDR;
+	u32 phy_id = smi->phy_id ? smi->phy_id : MDC_REALTEK_PHY_ADDR;
 	struct mii_bus *mbus = smi->ext_mbus;

 	BUG_ON(in_interrupt());
--- a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h
+++ b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h
@ -64,6 +64,7 @@ struct rtl8366_smi {
 	u8			dbg_vlan_4k_page;
 #endif
 	struct mii_bus		*ext_mbus;
+	u32			phy_id;
 };

 struct rtl8366_vlan_mc {
--- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c
+++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c
@ -213,6 +213,23 @@
 #define RTL8367B_RTL_MAGIC_ID_REG		0x13c2
 #define   RTL8367B_RTL_MAGIC_ID_VAL		0x0249

+#define RTL8367S_EXT_TXC_DLY_REG		0x13f9
+#define   RTL8367S_EXT1_GMII_TX_DELAY_SHIFT	12
+#define   RTL8367S_EXT0_GMII_TX_DELAY_SHIFT	9
+#define   RTL8367S_EXT_GMII_TX_DELAY_MASK	GENMASK(2,0)
+
+#define RTL8367S_SDS_MISC				0x1d11
+#define   RTL8367S_CFG_SGMII_RXFC		BIT(14)
+#define   RTL8367S_CFG_SGMII_TXFC		BIT(13)
+#define   RTL8367S_CFG_MAC8_SEL_HSGMII_SHIFT	11
+#define   RTL8367S_CFG_MAC8_SEL_HSGMII_MASK	BIT(11)
+#define   RTL8367S_CFG_SGMII_FDUP		BIT(10)
+#define   RTL8367S_CFG_SGMII_LINK		BIT(9)
+#define   RTL8367S_CFG_SGMII_SPD_SHIFT		7
+#define   RTL8367S_CFG_SGMII_SPD_MASK		GENMASK(8,7)
+#define   RTL8367S_CFG_MAC8_SEL_SGMII		BIT(6)
+
+
 #define RTL8367B_IA_CTRL_REG			0x1f00
 #define   RTL8367B_IA_CTRL_RW(_x)		((_x) << 1)
 #define   RTL8367B_IA_CTRL_RW_READ		RTL8367B_IA_CTRL_RW(0)
@ -230,9 +247,18 @@

 #define RTL8367B_INTERNAL_PHY_REG(_a, _r)	(0x2000 + 32 * (_a) + (_r))

+/* SerDes indirect access */
+#define RTL8367S_SDS_INDACS_CMD_REG		0x6600
+#define RTL8367S_SDS_CMD			BIT(7)
+#define RTL8367S_SDS_RWOP			BIT(6)
+#define RTL8367S_SDS_INDACS_ADDR_REG		0x6601
+#define RTL8367S_SDS_INDACS_DATA_REG		0x6602
+
 #define RTL8367B_NUM_MIB_COUNTERS	58

+#define RTL8367S_PHY_ADDR		29
 #define RTL8367B_CPU_PORT_NUM		5
+#define RTL8367S_CPU_PORT_NUM		7
 #define RTL8367B_NUM_PORTS		8
 #define RTL8367B_NUM_VLANS		32
 #define RTL8367B_NUM_VIDS		4096
@ -255,14 +281,16 @@

 #define RTL8367B_PORTS_ALL_BUT_CPU				\
 	(RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 |	\
-	 RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E1 |	\
-	 RTL8367B_PORT_E2)
+	 RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E0 |	\
+	 RTL8367B_PORT_E1)

 struct rtl8367b_initval {
 	u16 reg;
 	u16 val;
 };

+u32 rtl_device_id;
+
 #define RTL8367B_MIB_RXB_ID		0	/* IfInOctets */
 #define RTL8367B_MIB_TXB_ID		28	/* IfOutOctets */

@ -605,6 +633,45 @@ static const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = {
 	{0x133E, 0x000E}, {0x133F, 0x0010},
 };

+static const struct rtl8367b_initval rtl8367c_initvals0[] = {
+	{0x13c2, 0x0000}, {0x0018, 0x0f00}, {0x0038, 0x0f00}, {0x0058, 0x0f00},
+	{0x0078, 0x0f00}, {0x0098, 0x0f00}, {0x1d15, 0x0a69}, {0x2000, 0x1340},
+	{0x2020, 0x1340}, {0x2040, 0x1340}, {0x2060, 0x1340}, {0x2080, 0x1340},
+	{0x13eb, 0x15bb}, {0x1303, 0x06d6}, {0x1304, 0x0700}, {0x13E2, 0x003F},
+	{0x13F9, 0x0090}, {0x121e, 0x03CA}, {0x1233, 0x0352}, {0x1237, 0x00a0},
+	{0x123a, 0x0030}, {0x1239, 0x0084}, {0x0301, 0x1000}, {0x1349, 0x001F},
+	{0x18e0, 0x4004}, {0x122b, 0x641c}, {0x1305, 0xc000}, {0x1200, 0x7fcb},
+	{0x0884, 0x0003}, {0x06eb, 0x0001}, {0x00cf, 0xffff}, {0x00d0, 0x0007},
+	{0x00ce, 0x48b0}, {0x00ce, 0x48b0}, {0x0398, 0xffff}, {0x0399, 0x0007},
+	{0x0300, 0x0001}, {0x03fa, 0x0007}, {0x08c8, 0x00c0}, {0x0a30, 0x020e},
+	{0x0800, 0x0000}, {0x0802, 0x0000}, {0x09da, 0x0017}, {0x1d32, 0x0002},
+};
+static const struct rtl8367b_initval rtl8367s_initvals[] = {
+/* Special init for RTL8367SB in RGMII mode with some comments */
+/* phy port eee init */
+{0x0018, 0x0f00}, {0x1d15, 0x0a69}, {0x2014, 0x0000}, {0x2708, 0x0006},
+{0x0038, 0x0f00}, {0x1d15, 0x0a69}, {0x2034, 0x0000}, {0x2748, 0x0006},
+{0x0058, 0x0f00}, {0x1d15, 0x0a69}, {0x2054, 0x0000}, {0x2748, 0x0006},
+{0x0078, 0x0f00}, {0x1d15, 0x0a69}, {0x2074, 0x0000}, {0x2768, 0x0006},
+{0x0018, 0x0f00}, {0x1d15, 0x0a69}, {0x2094, 0x0000}, {0x2788, 0x0006},
+/* enable phy 0-4 - after reset phy is disabled */
+{0x1d15, 0x0a69}, {0x2000, 0x1340}, {0x2020, 0x1340}, {0x2040, 0x1340},
+{0x2060, 0x1340}, {0x2080, 0x1340},
+/* standard init */
+{0x13eb, 0x15bb}, {0x1303, 0x06d6}, {0x1304, 0x0700}, {0x13E2, 0x003F},
+{0x13F9, 0x0090},
+/* add init extended interface2 mode == rgmii explicitly */
+{0x1303, 0x0767}, {0x1304, 0x7777}, {0x1305, 0xc000}, {0x13E2, 0x01fd},
+{0x13c3, 0x0001}, {0x13c4, 0x1076}, {0x13c5, 0x000a},
+/*end init ext2 mode*/
+{0x121e, 0x03CA}, {0x1233, 0x0352}, {0x1237, 0x00a0}, {0x123a, 0x0030},
+{0x1239, 0x0084}, {0x0301, 0x1000}, {0x1349, 0x001F}, {0x18e0, 0x4004},
+{0x122b, 0x641c}, {0x1305, 0xc000}, {0x1200, 0x7fcb}, {0x0884, 0x0003},
+{0x06eb, 0x0001}, {0x00cf, 0xffff}, {0x00d0, 0x0007}, {0x00ce, 0x48b0},
+{0x0398, 0xffff}, {0x0399, 0x0007}, {0x0300, 0x0001}, {0x03fa, 0x0007},
+{0x08c8, 0x00c0}, {0x0a30, 0x020e}, {0x0800, 0x0000}, {0x0802, 0x0000},
+{0x09da, 0x0017}, {0x1d32, 0x0002}, {0x13c2, 0x0000}, 
+};
 static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
 				  const struct rtl8367b_initval *initvals,
 				  int count)
@ -612,6 +679,10 @@ static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
 	int err;
 	int i;

+	if (rtl_device_id == 0x0020) {
+		return 0;
+	}
+
 	for (i = 0; i < count; i++)
 		REG_WR(smi, initvals[i].reg, initvals[i].val);

@ -727,6 +798,11 @@ static int rtl8367b_init_regs(struct rtl8366_smi *smi)
 	rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &
 		RTL8367B_CHIP_VER_RLVID_MASK;

+	if (of_device_is_compatible(smi->parent->of_node,
+				    "realtek,rtl8367s")) {
+		initvals = rtl8367c_initvals0;
+		count = ARRAY_SIZE(rtl8367c_initvals0);
+	} else {
 	switch (rlvid) {
 	case 0:
 		initvals = rtl8367r_vb_initvals_0;
@ -742,9 +818,13 @@ static int rtl8367b_init_regs(struct rtl8366_smi *smi)
 		dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
 		return -ENODEV;
 	}
+	}

 	/* TODO: disable RLTP */

+	if(chip_ver == 0x0020)
+		return 0;
+
 	return rtl8367b_write_initvals(smi, initvals, count);
 }

@ -776,7 +856,45 @@ static int rtl8367b_reset_chip(struct rtl8366_smi *smi)
 static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
 				   enum rtl8367_extif_mode mode)
 {
-	int err;
+	int err, i;
+	/* for SGMII, works (from rtl8367s_api.c in TL-R600VPN v4 GPL) */
+	unsigned int redData[][2] = {
+		{0x7180, 0x2},
+		{0x04D7, 0x0480},
+		{0xF994, 0x0481},
+		{0x31A2, 0x0482},
+		{0x6960, 0x0483},
+		{0x9728, 0x0484},
+		{0x9D85, 0x0423},
+		{0xD810, 0x0424},
+		{0x0F80, 0x0001}
+	};
+
+	/*
+	 * for HSGMII, works
+	 * (from rtl8367c_asicdrv_port.c in TL-R600VPN v4 GPL,
+	 * based on redDataHB and customized like redData)
+	 */
+	unsigned int redDataH[][2] = {
+		{0x7180, 0x2},
+		{0x82F0, 0x0500},
+		{0xF195, 0x0501},
+		{0x31A2, 0x0502},
+		{0x7960, 0x0503},
+		{0x9728, 0x0504},
+		{0x9D85, 0x0423},
+		{0xD810, 0x0424},
+		{0x0F80, 0x0001},
+		{0x83F2, 0x002E}
+	};
+
+	if ((mode == RTL8367S_EXTIF_MODE_SGMII ||
+	     mode == RTL8367S_EXTIF_MODE_HSGMII)
+	     && id != RTL8367_EXTIF1) {
+		dev_err(smi->parent,
+			"SGMII/HSGMII mode is only available in extif1\n");
+		return -EINVAL;
+	}

 	/* set port mode */
 	switch (mode) {
@ -784,7 +902,7 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
 		REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
 			RTL8367B_DEBUG0_SEL33(id),
 			RTL8367B_DEBUG0_SEL33(id));
-		if (id <= 1) {
+		if (id <= RTL8367_EXTIF1) {
 			REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
 				RTL8367B_DEBUG0_DRI(id) |
 					RTL8367B_DEBUG0_DRI_RG(id) |
@ -820,6 +938,17 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
 			RTL8367B_DEBUG0_SEL33(id),
 			RTL8367B_DEBUG0_SEL33(id));
 		REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6));
+
+		if (of_device_is_compatible(smi->parent->of_node,
+					    "realtek,rtl8367s")) {
+			REG_RMW(smi, RTL8367S_EXT_TXC_DLY_REG,
+				RTL8367S_EXT_GMII_TX_DELAY_MASK
+					<< RTL8367S_EXT1_GMII_TX_DELAY_SHIFT |
+				RTL8367S_EXT_GMII_TX_DELAY_MASK
+					<< RTL8367S_EXT0_GMII_TX_DELAY_SHIFT,
+				5 << RTL8367S_EXT1_GMII_TX_DELAY_SHIFT |	/* shoud be configured */
+				6 << RTL8367S_EXT0_GMII_TX_DELAY_SHIFT);	/* in set_rgmii_delay? */
+		}
 		break;

 	case RTL8367_EXTIF_MODE_MII_MAC:
@ -829,13 +958,49 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
 		REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0);
 		break;

+	case RTL8367S_EXTIF_MODE_SGMII:
+		if (!of_device_is_compatible(smi->parent->of_node,
+					     "realtek,rtl8367s"))
+			goto invalid_mode;
+
+		/* setup SerDes register for SGMII */
+		for (i = 0; i <= 7; i++) {
+			REG_WR(smi, RTL8367S_SDS_INDACS_DATA_REG, redData[i][0]);
+			REG_WR(smi, RTL8367S_SDS_INDACS_ADDR_REG, redData[i][1]);
+			REG_WR(smi, RTL8367S_SDS_INDACS_CMD_REG,
+				RTL8367S_SDS_CMD | RTL8367S_SDS_RWOP);
+		}
+		break;
+
+	case RTL8367S_EXTIF_MODE_HSGMII:
+		if (!of_device_is_compatible(smi->parent->of_node,
+					     "realtek,rtl8367s"))
+			goto invalid_mode;
+
+		/* setup SerDes register for HSGMII */
+		for (i = 0; i <= 8; i++) {
+			REG_WR(smi, RTL8367S_SDS_INDACS_DATA_REG, redDataH[i][0]);
+			REG_WR(smi, RTL8367S_SDS_INDACS_ADDR_REG, redDataH[i][1]);
+			REG_WR(smi, RTL8367S_SDS_INDACS_CMD_REG,
+				RTL8367S_SDS_CMD | RTL8367S_SDS_RWOP);
+		}
+		break;
+
 	default:
-		dev_err(smi->parent,
-			"invalid mode for external interface %d\n", id);
-		return -EINVAL;
+		goto invalid_mode;
 	}

-	if (id <= 1)
+	if (id == RTL8367_EXTIF1 &&
+	    of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s")) {
+		REG_RMW(smi, RTL8367S_SDS_MISC,	RTL8367S_CFG_MAC8_SEL_HSGMII_MASK,
+			(mode == RTL8367S_EXTIF_MODE_HSGMII)
+				? RTL8367S_CFG_MAC8_SEL_HSGMII_MASK : 0);
+		REG_RMW(smi, RTL8367S_SDS_MISC,	RTL8367S_CFG_MAC8_SEL_SGMII,
+			(mode == RTL8367S_EXTIF_MODE_SGMII)
+				? RTL8367S_CFG_MAC8_SEL_SGMII : 0);
+	}
+
+	if (id <= RTL8367_EXTIF1)
 		REG_RMW(smi, RTL8367B_DIS_REG,
 			RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
 			mode << RTL8367B_DIS_RGMII_SHIFT(id));
@ -844,7 +1009,20 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
 			RTL8367B_DIS2_RGMII_MASK << RTL8367B_DIS2_RGMII_SHIFT,
 			mode << RTL8367B_DIS2_RGMII_SHIFT);

+	if (mode == RTL8367S_EXTIF_MODE_SGMII ||
+	    mode == RTL8367S_EXTIF_MODE_HSGMII) {
+		REG_WR(smi, RTL8367S_SDS_INDACS_DATA_REG, 0x7106);
+		REG_WR(smi, RTL8367S_SDS_INDACS_ADDR_REG, 0x0003);
+		REG_WR(smi, RTL8367S_SDS_INDACS_CMD_REG,
+				RTL8367S_SDS_CMD | RTL8367S_SDS_RWOP);
+	}
+
 	return 0;
+
+invalid_mode:
+	dev_err(smi->parent,
+		"invalid mode for external interface %d\n", id);
+	return -EINVAL;
 }

 static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
@ -854,6 +1032,20 @@ static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
 	u32 val;
 	int err;

+	if (id == RTL8367_EXTIF1 &&
+	    of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s")) {
+		REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_FDUP,
+			pa->duplex ? RTL8367S_CFG_SGMII_FDUP : 0);
+		REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_SPD_MASK,
+			pa->speed << RTL8367S_CFG_SGMII_SPD_SHIFT);
+		REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_LINK,
+			pa->link ? RTL8367S_CFG_SGMII_LINK : 0);
+		REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_TXFC,
+			pa->txpause ? RTL8367S_CFG_SGMII_TXFC : 0);
+		REG_RMW(smi, RTL8367S_SDS_MISC, RTL8367S_CFG_SGMII_RXFC,
+			pa->rxpause ? RTL8367S_CFG_SGMII_RXFC : 0);
+	}
+
 	mask = (RTL8367B_DI_FORCE_MODE |
 		RTL8367B_DI_FORCE_NWAY |
 		RTL8367B_DI_FORCE_TXPAUSE |
@ -915,6 +1107,15 @@ static int rtl8367b_extif_init(struct rtl8366_smi *smi, int id,
 						     cfg->rxdelay);
 		if (err)
 			return err;
+
+		if (of_device_is_compatible(smi->parent->of_node,
+					    "realtek,rtl8367s")) {
+			/* disable pre-emphasis */
+			REG_WR(smi, RTL8367S_SDS_INDACS_DATA_REG, 0x28A0);
+			REG_WR(smi, RTL8367S_SDS_INDACS_ADDR_REG, 0x0482);
+			REG_WR(smi, RTL8367S_SDS_INDACS_CMD_REG,
+					RTL8367S_SDS_CMD | RTL8367S_SDS_RWOP);
+		}
 	}

 	return 0;
@ -925,6 +1126,7 @@ static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
 				  const char *name)
 {
 	struct rtl8367_extif_config *cfg;
+	enum rtl8367_port_speed speed;
 	const __be32 *prop;
 	int size;
 	int err;
@ -950,7 +1152,11 @@ static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
 	cfg->ability.rxpause = be32_to_cpup(prop++);
 	cfg->ability.link = be32_to_cpup(prop++);
 	cfg->ability.duplex = be32_to_cpup(prop++);
-	cfg->ability.speed = be32_to_cpup(prop++);
+	speed = be32_to_cpup(prop++);
+	if (of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s") &&
+	    cfg->mode == RTL8367S_EXTIF_MODE_HSGMII)
+		speed = RTL8367_PORT_SPEED_1000;
+	cfg->ability.speed = speed;

 	err = rtl8367b_extif_init(smi, id, cfg);
 	kfree(cfg);
@ -979,23 +1185,28 @@ static int rtl8367b_setup(struct rtl8366_smi *smi)

 	/* initialize external interfaces */
 	if (smi->parent->of_node) {
-		err = rtl8367b_extif_init_of(smi, 0, "realtek,extif0");
+		err = rtl8367b_extif_init_of(smi, RTL8367_EXTIF0,
+					     "realtek,extif0");
 		if (err)
 			return err;

-		err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1");
+		err = rtl8367b_extif_init_of(smi, RTL8367_EXTIF1,
+					     "realtek,extif1");
 		if (err)
 			return err;

-		err = rtl8367b_extif_init_of(smi, 2, "realtek,extif2");
+		err = rtl8367b_extif_init_of(smi, RTL8367_EXTIF2,
+					     "realtek,extif2");
 		if (err)
 			return err;
 	} else {
-		err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);
+		err = rtl8367b_extif_init(smi, RTL8367_EXTIF0,
+					  pdata->extif0_cfg);
 		if (err)
 			return err;

-		err = rtl8367b_extif_init(smi, 1, pdata->extif1_cfg);
+		err = rtl8367b_extif_init(smi, RTL8367_EXTIF1,
+					  pdata->extif1_cfg);
 		if (err)
 			return err;
 	}
@ -1270,12 +1481,16 @@ static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
 				    struct switch_port_link *link)
 {
 	struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
-	u32 data = 0;
+	u32 data = 0, sds_misc = 0;
 	u32 speed;

 	if (port >= RTL8367B_NUM_PORTS)
 		return -EINVAL;

+	if (port == 6 &&
+		of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s"))
+		rtl8366_smi_read_reg(smi, RTL8367S_SDS_MISC, &sds_misc);
+
 	rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);

 	link->link = !!(data & RTL8367B_PORT_STATUS_LINK);
@ -1296,7 +1511,10 @@ static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
 		link->speed = SWITCH_PORT_SPEED_100;
 		break;
 	case 2:
-		link->speed = SWITCH_PORT_SPEED_1000;
+		link->speed = (((sds_misc & RTL8367S_CFG_MAC8_SEL_HSGMII_MASK)
+				>> RTL8367S_CFG_MAC8_SEL_HSGMII_SHIFT) == 1)
+				? SWITCH_PORT_SPEED_2500
+				: SWITCH_PORT_SPEED_1000;
 		break;
 	default:
 		link->speed = SWITCH_PORT_SPEED_UNKNOWN;
@ -1540,7 +1758,20 @@ static int rtl8367b_detect(struct rtl8366_smi *smi)
 		return ret;
 	}

+	dev_info(smi->parent,
+		"found chip num:%04x ver:%04x, mode:%04x\n",
+		chip_num, chip_ver, chip_mode);
+
+	/* rtl8367s: known chip num:6367 ver:00a0, mode:00a0 */
+
+	if (of_device_is_compatible(smi->parent->of_node, "realtek,rtl8367s")) {
+		if (chip_ver == 0x00a0)
+			chip_name = "8367S";
+		else
+			goto unknown_chip;
+	} else {
 	switch (chip_ver) {
+	case 0x0020:
 	case 0x1000:
 		chip_name = "8367RB";
 		break;
@ -1548,15 +1779,19 @@ static int rtl8367b_detect(struct rtl8366_smi *smi)
 		chip_name = "8367R-VB";
 		break;
 	default:
-		dev_err(smi->parent,
-			"unknown chip num:%04x ver:%04x, mode:%04x\n",
-			chip_num, chip_ver, chip_mode);
-		return -ENODEV;
+			goto unknown_chip;
+		}
 	}

 	dev_info(smi->parent, "RTL%s chip found\n", chip_name);

 	return 0;
+
+unknown_chip:
+	dev_err(smi->parent,
+		"unknown chip num:%04x ver:%04x, mode:%04x\n",
+		chip_num, chip_ver, chip_mode);
+	return -ENODEV;
 }

 static struct rtl8366_smi_ops rtl8367b_smi_ops = {
@ -1595,11 +1830,17 @@ static int  rtl8367b_probe(struct platform_device *pdev)
 	smi->ops = &rtl8367b_smi_ops;
 	smi->num_ports = RTL8367B_NUM_PORTS;
 	if (of_property_read_u32(pdev->dev.of_node, "cpu_port", &smi->cpu_port)
-	    || smi->cpu_port >= smi->num_ports)
+	    || smi->cpu_port >= smi->num_ports) {
+		if (of_device_is_compatible(pdev->dev.of_node, "realtek,rtl8367s"))
+			smi->cpu_port = RTL8367S_CPU_PORT_NUM;
+		else
 		smi->cpu_port = RTL8367B_CPU_PORT_NUM;
+	}
 	smi->num_vlan_mc = RTL8367B_NUM_VLANS;
 	smi->mib_counters = rtl8367b_mib_counters;
 	smi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters);
+	if (of_device_is_compatible(pdev->dev.of_node, "realtek,rtl8367s"))
+		smi->phy_id = RTL8367S_PHY_ADDR;

 	err = rtl8366_smi_init(smi);
 	if (err)
@ -1646,6 +1887,7 @@ static void rtl8367b_shutdown(struct platform_device *pdev)
 #ifdef CONFIG_OF
 static const struct of_device_id rtl8367b_match[] = {
 	{ .compatible = "realtek,rtl8367b" },
+	{ .compatible = "realtek,rtl8367s" },
 	{},
 };
 MODULE_DEVICE_TABLE(of, rtl8367b_match);
--- a/target/linux/generic/files/include/linux/rtl8367.h
+++ b/target/linux/generic/files/include/linux/rtl8367.h
@ -18,6 +18,8 @@ enum rtl8367_port_speed {
 	RTL8367_PORT_SPEED_10 = 0,
 	RTL8367_PORT_SPEED_100,
 	RTL8367_PORT_SPEED_1000,
+	RTL8367S_PORT_SPEED_500M,
+	RTL8367S_PORT_SPEED_2500M,
 };

 struct rtl8367_port_ability {
@ -30,6 +32,12 @@ struct rtl8367_port_ability {
 	enum rtl8367_port_speed speed;
 };

+enum rtl8367_extif {
+	RTL8367_EXTIF0 = 0,
+	RTL8367_EXTIF1,
+	RTL8367_EXTIF2,
+};
+
 enum rtl8367_extif_mode {
 	RTL8367_EXTIF_MODE_DISABLED = 0,
 	RTL8367_EXTIF_MODE_RGMII,
@ -39,9 +47,11 @@ enum rtl8367_extif_mode {
 	RTL8367_EXTIF_MODE_TMII_PHY,
 	RTL8367_EXTIF_MODE_GMII,
 	RTL8367_EXTIF_MODE_RGMII_33V,
-	RTL8367B_EXTIF_MODE_RMII_MAC = 7,
+	RTL8367B_EXTIF_MODE_RMII_MAC,
 	RTL8367B_EXTIF_MODE_RMII_PHY,
 	RTL8367B_EXTIF_MODE_RGMII_33V,
+	RTL8367S_EXTIF_MODE_SGMII,
+	RTL8367S_EXTIF_MODE_HSGMII,
 };

 struct rtl8367_extif_config {
--- a/target/linux/generic/files/include/linux/switch.h
+++ b/target/linux/generic/files/include/linux/switch.h
@ -45,6 +45,7 @@ enum switch_port_speed {
 	SWITCH_PORT_SPEED_10 = 10,
 	SWITCH_PORT_SPEED_100 = 100,
 	SWITCH_PORT_SPEED_1000 = 1000,
+	SWITCH_PORT_SPEED_2500 = 2500,
 };

 struct switch_port_link {
--- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
+++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
@ -15,6 +15,10 @@ rockchip_setup_interfaces()
 	xunlong,orangepi-r1-plus-lts)
 		ucidef_set_interfaces_lan_wan 'eth1' 'eth0'
 		;;
+	aio,aio-3399b)
+		ucidef_add_switch "switch0" \
+			"7@eth0" "0:lan:0" "1:lan:1" "2:lan:2" "3:lan:3" "4:lan:4" "5:lan:5" "6:wan:6"
+		;;
 	*)
 		ucidef_set_interface_lan 'eth0'
 		;;
@ -62,6 +66,13 @@ rockchip_setup_macs()
 		wan_mac=$(macaddr_generate_from_mmc_cid mmcblk0)
 		lan_mac=$(macaddr_add "$wan_mac" 1)
 		;;
+	aio,aio-3399b)
+	[ -d /sys/class/block/mmcblk0/mmcblk0boot0 ]&&mmcnb=mmcblk0
+	[ -d /sys/class/block/mmcblk1/mmcblk1boot0 ]&&mmcnb=mmcblk1
+	[ -d /sys/class/block/mmcblk2/mmcblk2boot0 ]&&mmcnb=mmcblk2
+		wan_mac=$(macaddr_generate_from_mmc_cid $mmcnb)
+		lan_mac=$(macaddr_add "$wan_mac" +1)
+		;;
 	friendlyarm,nanopi-r4s|\
 	friendlyarm,nanopi-r4se)
 		wan_mac=$(nanopi_r4s_get_mac wan)
--- a/target/linux/rockchip/armv8/base-files/etc/uci-defaults/13_pon_config
+++ b/target/linux/rockchip/armv8/base-files/etc/uci-defaults/13_pon_config
@ -0,0 +1,25 @@
+#!/bin/sh
+board=$(cat /tmp/sysinfo/board_name)
+case "$board" in
+aio,aio-3399b)
+uci -q set network.lan.ipaddr="192.168.9.1"
+uci -q set network.pon=interface
+uci -q set network.pon.proto="static"
+uci -q set network.pon.device="eth0.2"
+uci -q set network.pon.delegate="0"
+uci -q set network.pon.ipaddr="192.168.1.254"
+uci -q set network.pon.netmask="255.255.255.0"
+uci -q set network.pon.metric="100"
+uci -q set network.pon_route=route
+uci -q set network.pon_route.interface='pon'
+uci -q set network.pon_route.target='192.168.1.10'
+uci -q set network.pon_route.netmask='255.255.255.0'
+uci -q set network.pon_route.gateway='192.168.1.254'
+uci -q set network.pon_route.metric='100'
+uci -q commit network
+;;
+*)
+exit 0
+;;
+esac
+exit 0
--- a/target/linux/rockchip/armv8/config-5.15
+++ b/target/linux/rockchip/armv8/config-5.15
@ -517,6 +517,7 @@ CONFIG_SCSI_SAS_HOST_SMP=y
 CONFIG_SCSI_SAS_LIBSAS=y
 # CONFIG_SECURITY_DMESG_RESTRICT is not set
 CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_SENSORS_PWM_FAN=y
 CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_DWLIB=y
--- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-aio-3399b.dts
+++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-aio-3399b.dts
--- a/target/linux/rockchip/files/drivers/net/phy/motorcomm.c
+++ b/target/linux/rockchip/files/drivers/net/phy/motorcomm.c
@ -1,414 +0,0 @@
-/*
- * drivers/net/phy/motorcomm.c
- *
- * Driver for Motorcomm PHYs
- *
- * Author: Leilei Zhao <leilei.zhao@motorcomm.com>
- *
- * Copyright (c) 2019 Motorcomm, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * Support : Motorcomm Phys:
- *		Giga phys: yt8511, yt8521
- *		100/10 Phys : yt8512, yt8512b, yt8510
- *		Automotive 100Mb Phys : yt8010
- *		Automotive 100/10 hyper range Phys: yt8510
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/phy.h>
-#include <linux/motorcomm_phy.h>
-#include <linux/of.h>
-#include <linux/clk.h>
-
-static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
-{
-	int ret;
-	int val;
-
-	ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
-	if (ret < 0)
-		return ret;
-
-	val = phy_read(phydev, REG_DEBUG_DATA);
-
-	return val;
-}
-
-static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
-{
-	int ret;
-
-	ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
-	if (ret < 0)
-		return ret;
-
-	ret = phy_write(phydev, REG_DEBUG_DATA, val);
-
-	return ret;
-}
-
-static int yt8010_config_aneg(struct phy_device *phydev)
-{
-	phydev->speed = SPEED_100;
-	return 0;
-}
-
-static int yt8511_config_init(struct phy_device *phydev)
-{
-	int ret;
-	int val;
-
-	/* disable auto sleep */
-	val = ytphy_read_ext(phydev, YT8511_EXTREG_SLEEP_CONTROL1);
-	if (val < 0)
-		return val;
-
-	val &= (~BIT(YT8511_EN_SLEEP_SW_BIT));
-	ret = ytphy_write_ext(phydev, YT8511_EXTREG_SLEEP_CONTROL1, val);
-	if (ret < 0)
-		return ret;
-
-	/* output SyncE clock (125mhz) even link is down */
-	ret = ytphy_write_ext(phydev, 0xa012, 0xd0);
-	if (ret < 0)
-		return ret;
-
-	/* enable RXC clock when no wire plug */
-	val = ytphy_read_ext(phydev, 0xc);
-	if (val < 0)
-		return val;
-
-	/* ext reg 0xc.b[2:1]
-	00-----25M from pll;
-	01---- 25M from xtl;(default)
-	10-----62.5M from pll;
-	11----125M from pll(here set to this value)
-	*/
-	val |= (3 << 1);
-	ret = ytphy_write_ext(phydev, 0xc, val);
-	if (ret < 0)
-		return ret;
-
-	/* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */
-	ytphy_write_ext(phydev, 0xa00b, 0xe004);
-	ytphy_write_ext(phydev, 0xa00c, 0);
-	ytphy_write_ext(phydev, 0xa00d, 0x2600);
-	ytphy_write_ext(phydev, 0xa00e, 0x0070);
-	ytphy_write_ext(phydev, 0xa00f, 0x000a);
-
-	return 0;
-}
-
-static int yt8512_clk_init(struct phy_device *phydev)
-{
-	int ret;
-	int val;
-
-	val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL);
-	if (val < 0)
-		return val;
-
-	val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN;
-
-	ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val);
-	if (ret < 0)
-		return ret;
-
-	val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO);
-	if (val < 0)
-		return val;
-
-	val |= YT8512_CONTROL1_RMII_EN;
-
-	ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val);
-	if (ret < 0)
-		return ret;
-
-	val = phy_read(phydev, MII_BMCR);
-	if (val < 0)
-		return val;
-
-	val |= YT_SOFTWARE_RESET;
-	ret = phy_write(phydev, MII_BMCR, val);
-
-	return ret;
-}
-
-static int yt8512_led_init(struct phy_device *phydev)
-{
-	int ret;
-	int val;
-	int mask;
-
-	val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);
-	if (val < 0)
-		return val;
-
-	val |= YT8512_LED0_ACT_BLK_IND;
-
-	mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |
-		YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |
-		YT8512_LED0_BT_ON_EN;
-	val &= ~mask;
-
-	ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);
-	if (ret < 0)
-		return ret;
-
-	val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);
-	if (val < 0)
-		return val;
-
-	val |= YT8512_LED1_BT_ON_EN;
-
-	mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;
-	val &= ~mask;
-
-	ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val);
-
-	return ret;
-}
-
-static int yt8512_config_init(struct phy_device *phydev)
-{
-	int ret;
-	int val;
-
-	ret = yt8512_clk_init(phydev);
-	if (ret < 0)
-		return ret;
-
-	ret = yt8512_led_init(phydev);
-
-	/* disable auto sleep */
-	val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);
-	if (val < 0)
-		return val;
-
-	val &= (~BIT(YT8512_EN_SLEEP_SW_BIT));
-
-	ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);
-	if (ret < 0)
-		return ret;
-
-	return ret;
-}
-
-static int yt8512_read_status(struct phy_device *phydev)
-{
-	int ret;
-	int val;
-	int speed, speed_mode, duplex;
-
-	ret = genphy_update_link(phydev);
-	if (ret)
-		return ret;
-
-	val = phy_read(phydev, REG_PHY_SPEC_STATUS);
-	if (val < 0)
-		return val;
-
-	duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT;
-	speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT;
-	switch (speed_mode) {
-	case 0:
-		speed = SPEED_10;
-		break;
-	case 1:
-		speed = SPEED_100;
-		break;
-	case 2:
-	case 3:
-	default:
-		speed = SPEED_UNKNOWN;
-		break;
-	}
-
-	phydev->speed = speed;
-	phydev->duplex = duplex;
-
-	return 0;
-}
-
-static int yt8521_config_init(struct phy_device *phydev)
-{
-	int ret;
-	int val;
-
-	/* disable auto sleep */
-	val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
-	if (val < 0)
-		return val;
-
-	val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
-	ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
-	if (ret < 0)
-		return ret;
-
-	/* switch to access UTP */
-	ret = ytphy_write_ext(phydev, 0xa000, 0);
-	if (ret < 0)
-		return ret;
-
-	/* enable RXC clock when no wire plug */
-	val = ytphy_read_ext(phydev, 0xc);
-	if (val < 0)
-		return val;
-
-	val &= ~(1 << 12);
-	ret = ytphy_write_ext(phydev, 0xc, val);
-	if (ret < 0)
-		return ret;
-
-	/* output SyncE clock (125mhz) even link is down */
-	ret = ytphy_write_ext(phydev, 0xa012, 0x38);
-	if (ret < 0)
-		return ret;
-
-	/* disable rgmii clk 2ns delay */
-	val = ytphy_read_ext(phydev, 0xa001);
-	if (val < 0)
-		return val;
-
-	val &= ~(1 << 8);
-	ret = ytphy_write_ext(phydev, 0xa001, val);
-	if (ret < 0)
-		return ret;
-
-	/* setup delay */
-	val = (1 << 10) | (0xf << 4) | 5;
-	ret = ytphy_write_ext(phydev, 0xa003, val);
-	if (ret < 0)
-		return ret;
-
-	/* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */
-	ytphy_write_ext(phydev, 0xa00b, 0xe004);
-	ytphy_write_ext(phydev, 0xa00c, 0);
-	ytphy_write_ext(phydev, 0xa00d, 0x2600);
-	ytphy_write_ext(phydev, 0xa00e, 0x0070);
-	ytphy_write_ext(phydev, 0xa00f, 0x000a);
-
-	return 0;
-}
-
-static int yt8521_config_intr(struct phy_device *phydev)
-{
-	int val;
-
-	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
-		val = BIT(14) | BIT(13) | BIT(11) | BIT(10);
-	else
-		val = 0;
-
-	return phy_write(phydev, REG_INT_MASK, val);
-}
-
-static int yt8521_ack_interrupt(struct phy_device *phydev)
-{
-	int val;
-
-	val = phy_read(phydev, REG_INT_STATUS);
-	phydev_dbg(phydev, "intr status 0x04%x\n", val);
-
-	return (val < 0) ? val : 0;
-}
-
-static struct phy_driver ytphy_drvs[] = {
-	{
-		.phy_id		= PHY_ID_YT8010,
-		.name		= "YT8010 Automotive Ethernet",
-		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-		.features	= PHY_BASIC_FEATURES,
-		.config_aneg	= yt8010_config_aneg,
-		.read_status	= genphy_read_status,
-	}, {
-		.phy_id		= PHY_ID_YT8510,
-		.name		= "YT8510 100/10Mb Ethernet",
-		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-		.features	= PHY_BASIC_FEATURES,
-		.read_status	= genphy_read_status,
-	}, {
-		.phy_id		= PHY_ID_YT8511,
-		.name		= "YT8511 Gigabit Ethernet",
-		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-		.features	= PHY_GBIT_FEATURES,
-		.read_status	= genphy_read_status,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-	}, {
-		.phy_id		= PHY_ID_YT8512,
-		.name		= "YT8512 Ethernet",
-		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-		.features	= PHY_BASIC_FEATURES,
-		.config_init	= yt8512_config_init,
-		.read_status	= yt8512_read_status,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-	}, {
-		.phy_id		= PHY_ID_YT8512B,
-		.name		= "YT8512B Ethernet",
-		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-		.features	= PHY_BASIC_FEATURES,
-		.config_init	= yt8512_config_init,
-		.read_status	= yt8512_read_status,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-	}, {
-		.phy_id		= PHY_ID_YT8521,
-		.name		= "YT8521 Ethernet",
-		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-		/* PHY_GBIT_FEATURES */
-		.config_init	= yt8521_config_init,
-		.ack_interrupt	= yt8521_ack_interrupt,
-		.config_intr	= yt8521_config_intr,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-	}, {
-		/* same as 8521 */
-		.phy_id		= PHY_ID_YT8531S,
-		.name		= "YT8531S Ethernet",
-		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-		/* PHY_GBIT_FEATURES */
-		.config_init	= yt8521_config_init,
-		.ack_interrupt	= yt8521_ack_interrupt,
-		.config_intr	= yt8521_config_intr,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-	}, {
-		/* same as 8511 */
-		.phy_id		= PHY_ID_YT8531,
-		.name		= "YT8531 Gigabit Ethernet",
-		.phy_id_mask	= MOTORCOMM_PHY_ID_MASK,
-		.features	= PHY_GBIT_FEATURES,
-		.config_init	= yt8511_config_init,
-		.read_status	= genphy_read_status,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-	},
-};
-
-module_phy_driver(ytphy_drvs);
-
-MODULE_DESCRIPTION("Motorcomm PHY driver");
-MODULE_AUTHOR("Leilei Zhao");
-MODULE_LICENSE("GPL");
-
-static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
-	{ PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK },
-	{ PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK },
-	{ PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK },
-	{ PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },
-	{ PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },
-	{ PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },
-	{ PHY_ID_YT8531S, MOTORCOMM_PHY_ID_8531_MASK },
-	{ PHY_ID_YT8531, MOTORCOMM_PHY_ID_8531_MASK },
-	{ }
-};
-
-MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
--- a/target/linux/rockchip/files/include/linux/motorcomm_phy.h
+++ b/target/linux/rockchip/files/include/linux/motorcomm_phy.h
@ -1,73 +0,0 @@
-/*
- * include/linux/motorcomm_phy.h
- *
- * Motorcomm PHY IDs
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifndef _MOTORCOMM_PHY_H
-#define _MOTORCOMM_PHY_H
-
-#define MOTORCOMM_PHY_ID_MASK	0x00000fff
-#define MOTORCOMM_PHY_ID_8531_MASK	0xffffffff
-
-#define PHY_ID_YT8010		0x00000309
-#define PHY_ID_YT8510		0x00000109
-#define PHY_ID_YT8511		0x0000010a
-#define PHY_ID_YT8512		0x00000118
-#define PHY_ID_YT8512B		0x00000128
-#define PHY_ID_YT8521		0x0000011a
-#define PHY_ID_YT8531S		0x4f51e91a
-#define PHY_ID_YT8531		0x4f51e91b
-
-#define REG_PHY_SPEC_STATUS		0x11
-#define REG_INT_MASK			0x12
-#define REG_INT_STATUS			0x13
-#define REG_DEBUG_ADDR_OFFSET		0x1e
-#define REG_DEBUG_DATA			0x1f
-
-#define YT8511_EXTREG_SLEEP_CONTROL1	0x27
-#define YT8511_EN_SLEEP_SW_BIT		15
-
-#define YT8512_EXTREG_AFE_PLL		0x50
-#define YT8512_EXTREG_EXTEND_COMBO	0x4000
-#define YT8512_EXTREG_LED0		0x40c0
-#define YT8512_EXTREG_LED1		0x40c3
-
-#define YT8512_EXTREG_SLEEP_CONTROL1	0x2027
-
-#define YT_SOFTWARE_RESET		0x8000
-
-#define YT8512_CONFIG_PLL_REFCLK_SEL_EN	0x0040
-#define YT8512_CONTROL1_RMII_EN		0x0001
-#define YT8512_LED0_ACT_BLK_IND		0x1000
-#define YT8512_LED0_DIS_LED_AN_TRY	0x0001
-#define YT8512_LED0_BT_BLK_EN		0x0002
-#define YT8512_LED0_HT_BLK_EN		0x0004
-#define YT8512_LED0_COL_BLK_EN		0x0008
-#define YT8512_LED0_BT_ON_EN		0x0010
-#define YT8512_LED1_BT_ON_EN		0x0010
-#define YT8512_LED1_TXACT_BLK_EN	0x0100
-#define YT8512_LED1_RXACT_BLK_EN	0x0200
-#define YT8512_SPEED_MODE		0xc000
-#define YT8512_DUPLEX			0x2000
-
-#define YT8512_SPEED_MODE_BIT		14
-#define YT8512_DUPLEX_BIT		13
-#define YT8512_EN_SLEEP_SW_BIT		15
-
-#define YT8521_EXTREG_SLEEP_CONTROL1	0x27
-#define YT8521_EN_SLEEP_SW_BIT		15
-
-#define YT8521_SPEED_MODE		0xc000
-#define YT8521_DUPLEX			0x2000
-#define YT8521_SPEED_MODE_BIT		14
-#define YT8521_DUPLEX_BIT		13
-#define YT8521_LINK_STATUS_BIT		10
-
-#endif /* _MOTORCOMM_PHY_H */
--- a/target/linux/rockchip/image/Makefile
+++ b/target/linux/rockchip/image/Makefile
@ -44,6 +44,26 @@ define Build/pine64-img
 	dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-u-boot.itb of="$@" seek=16384 conv=notrunc
 endef

+define Build/pine64-bin
+	# Typical Rockchip boot flow with Rockchip miniloader
+	# Rockchp idbLoader which is combinded by Rockchip ddr init bin
+	# and miniloader bin from Rockchip rkbin project
+
+	# Generate a new partition table in $@ with 32 MiB of alignment
+	# padding for the idbloader, uboot and trust image to fit:
+	# http://opensource.rock-chips.com/wiki_Boot_option#Boot_flow
+	PADDING=1 $(SCRIPT_DIR)/gen_image_generic.sh \
+		$@ \
+		$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
+		$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
+		32768
+
+	# Copy the idbloader, uboot and trust image to the image at sector 0x40, 0x4000 and 0x6000
+	dd if="$(STAGING_DIR_IMAGE)"/$(SOC)-idbloader.bin of="$@" seek=64 conv=notrunc
+	dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-uboot.img of="$@" seek=16384 conv=notrunc
+	dd if="$(STAGING_DIR_IMAGE)"/$(SOC)-trust.bin of="$@" seek=24576 conv=notrunc
+endef
+
 ### Devices ###
 define Device/Default
  PROFILES := Default
--- a/target/linux/rockchip/image/armv8.mk
+++ b/target/linux/rockchip/image/armv8.mk
@ -15,6 +15,14 @@ define Device/firefly_roc-rk3328-cc
 endef
 TARGET_DEVICES += firefly_roc-rk3328-cc

+define Device/aio-3399b
+  DEVICE_VENDOR := AllInOne
+  DEVICE_MODEL := AIO-3399B
+  SOC := rk3399
+  IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-bin | gzip | append-metadata
+  DEVICE_PACKAGES := kmod-brcmfmac brcmfmac-nvram-4356-sdio cypress-firmware-4356-sdio swconfig kmod-ata-ahci kmod-nvme  aio-3399b-firmware kmod-switch-rtl8367b wpad-openssl ethtool
+endef
+TARGET_DEVICES += aio-3399b
 define Device/friendlyarm_nanopi-r2c
  DEVICE_VENDOR := FriendlyARM
  DEVICE_MODEL := NanoPi R2C
--- a/target/linux/rockchip/patches-5.15/213-rockchip-rk3399-add-support-for-aio-3399b.patch
+++ b/target/linux/rockchip/patches-5.15/213-rockchip-rk3399-add-support-for-aio-3399b.patch
@ -0,0 +1,10 @@
+--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -45,6 +45,7 @@
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-aio-3399b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb
--- a/target/linux/rockchip/patches-5.15/303-rk33xx-dwc3-parkmode-disable-ss-quirk.patch
+++ b/target/linux/rockchip/patches-5.15/303-rk33xx-dwc3-parkmode-disable-ss-quirk.patch
@ -1,10 +0,0 @@
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -1048,6 +1048,7 @@
- 			snps,dis_u3_susphy_quirk;
- 			snps,dis-del-phy-power-chg-quirk;
- 			snps,dis-tx-ipgap-linecheck-quirk;
-+			snps,parkmode-disable-ss-quirk;
- 			status = "disabled";
- 		};
- 	};
--- a/target/linux/rockchip/patches-5.15/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch
+++ b/target/linux/rockchip/patches-5.15/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch
@ -1,39 +0,0 @@
-From 5d6862cc5eac1679d7a4ef388f7c9bbc70e76770 Mon Sep 17 00:00:00 2001
-From: hmz007 <hmz007@gmail.com>
-Date: Mon, 5 Jul 2021 17:03:00 +0800
-Subject: [PATCH] net: phy: Add driver for Motorcomm YT85xx PHYs
-
-Signed-off-by: hmz007 <hmz007@gmail.com>
---
- drivers/net/phy/Kconfig       |   5 +
- drivers/net/phy/Makefile      |   1 +
- drivers/net/phy/motorcomm.c   | 346 ++++++++++++++++++++++++++++++++++
- include/linux/motorcomm_phy.h |  68 +++++++
- 4 files changed, 420 insertions(+)
- create mode 100644 drivers/net/phy/motorcomm.c
- create mode 100644 include/linux/motorcomm_phy.h
-
--- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -302,6 +302,11 @@ config MICROSEMI_PHY
- 	help
- 	  Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
- 
-+config MOTORCOMM_PHY
-+	tristate "Motorcomm PHYs"
-+	help
-+	  Supports the YT8010, YT8510, YT8511, YT8512 PHYs.
-+
- config NATIONAL_PHY
- 	tristate "National Semiconductor PHYs"
- 	help
--- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -83,6 +83,7 @@ obj-$(CONFIG_MICREL_PHY)	+= micrel.o
- obj-$(CONFIG_MICROCHIP_PHY)	+= microchip.o
- obj-$(CONFIG_MICROCHIP_T1_PHY)	+= microchip_t1.o
- obj-$(CONFIG_MICROSEMI_PHY)	+= mscc/
-+obj-$(CONFIG_MOTORCOMM_PHY)	+= motorcomm.o
- obj-$(CONFIG_NATIONAL_PHY)	+= national.o
- obj-$(CONFIG_NXP_TJA11XX_PHY)	+= nxp-tja11xx.o
- obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
--- a/target/linux/rockchip/patches-5.15/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch
+++ b/target/linux/rockchip/patches-5.15/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch
@ -1,52 +0,0 @@
-From faa767a9d0ced5642da0ae50b53d87de258f9525 Mon Sep 17 00:00:00 2001
-From: hmz007 <hmz007@gmail.com>
-Date: Tue, 19 Nov 2019 17:24:30 +0800
-Subject: [PATCH] phy: rockchip: add driver for Rockchip USB 3.0 PHY
-
-Signed-off-by: hmz007 <hmz007@gmail.com>
---
- drivers/phy/rockchip/Kconfig                  |    8 +
- drivers/phy/rockchip/Makefile                 |    1 +
- drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 1175 +++++++++++++++++
- 3 files changed, 1184 insertions(+)
- create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c
-
--- a/drivers/phy/rockchip/Kconfig
-+++ b/drivers/phy/rockchip/Kconfig
-@@ -56,6 +56,15 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
- 	  Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
- 	  Innosilicon IP block.
- 
-+config PHY_ROCKCHIP_INNO_USB3
-+	tristate "Rockchip INNO USB 3.0 PHY Driver"
-+	depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
-+	depends on USB_SUPPORT
-+	select GENERIC_PHY
-+	select USB_PHY
-+	help
-+	  Support for Rockchip USB 3.0 PHY with Innosilicon IP block.
-+
- config PHY_ROCKCHIP_PCIE
- 	tristate "Rockchip PCIe PHY Driver"
- 	depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
--- a/drivers/phy/rockchip/Makefile
-+++ b/drivers/phy/rockchip/Makefile
-@@ -5,6 +5,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_EMMC)		+= phy-
- obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
- obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
- obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
-+obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3)	+= phy-rockchip-inno-usb3.o
- obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
- obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
- obj-$(CONFIG_PHY_ROCKCHIP_USB)		+= phy-rockchip-usb.o
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
-+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
-@@ -45,6 +45,8 @@ Required Properties:
-    - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
- - compatible: USBGRF should be one of the following:
-    - "rockchip,rv1108-usbgrf", "syscon": for rv1108
-+- compatible: USB3PHYGRF should be one of the following:
-+   - "rockchip,u3phy-grf", "syscon"
- - reg: physical base address of the controller and length of memory mapped
-   region.
- 
--- a/tools/tar/Makefile
+++ b/tools/tar/Makefile
@ -4,6 +4,7 @@
 # This is free software, licensed under the GNU General Public License v2.
 # See /LICENSE for more information.
 #
+export FORCE_UNSAFE_CONFIGURE=1
 include $(TOPDIR)/rules.mk

 PKG_NAME:=tar